公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US5453390A

公开(公告)日：1995-09-26

申请号：US38958

申请日：1993-03-29

申请人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

发明人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L21/266

CPC分类号： H01L29/66712 ,  H01L27/0248 ,  H01L29/7811 ,  H01L29/7815 ,  Y10S148/126

摘要： A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.

摘要翻译： 一种具有电流检测功能的功率半导体器件，包括具有比主要电流部分更好的达到耐受电压能力的元件的检测灵敏度。 功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。 设备的一个区域作为检测部分，另一个作为主要的当前部分。 检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。 低密度层的表面分别载有第二导电类型的主要和次要的阱区。 主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。 通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。 这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

公开(公告)号：US6015737A

公开(公告)日：2000-01-18

申请号：US515176

申请日：1995-08-15

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/4236

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： 垂直型功率MOSFET可显着降低每个区域的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US5776812A

公开(公告)日：1998-07-07

申请号：US413410

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/045 ,  H01L29/7813 ,  H01L29/4236

摘要： A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.

摘要翻译： 一种MOSFET的制造方法，其具有在槽的侧面上的通道部分，其不允许将缺陷或污染物引入通道部分中并且可以使槽的形状均匀。 在n +型半导体衬底的主表面上形成具有低杂质浓度的n型外延层。 该表面被指定为主表面，并且化学干蚀刻被施加到该主表面的指定区域。 包括通过化学干蚀刻生成的表面的区域被选择性地氧化以形成具有特定厚度的选择性氧化膜。 在该过程之后，p型和n型杂质从主表面双重扩散以限定通道的长度并形成基层和源层。 此外，n +型半导体衬底被指定为漏极层。 在双扩散之后，通过栅极氧化膜形成栅电极，形成源电极和漏电极。

公开(公告)号：US5365085A

公开(公告)日：1994-11-15

申请号：US735512

申请日：1991-07-29

申请人： Norihito Tokura ,  Tsuyoshi Yamamoto

发明人： Norihito Tokura ,  Tsuyoshi Yamamoto

IPC分类号： G05F1/56 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111 ,  H01L29/00 ,  H01L27/082

CPC分类号： H01L29/7813 ,  H01L27/0248 ,  H01L29/7815

摘要： A power semiconductor device constituted of a MOSFET incorporating a current detecting function for detecting current making use of a voltage drop developed across a channel resistance in which variations in the channel resistance due to its temperature and the gate voltage are compensated for and thereby highly accurate current detection is achieved.

摘要翻译： 一种功率半导体器件，其由具有电流检测功能的MOSFET构成，该MOSFET用于检测利用在沟道电阻上产生的电压降的电流，其中由于其温度和栅极电压导致的沟道电阻的变化被补偿，并由此高精度的电流 实现检测。

公开(公告)号：US5698880A

公开(公告)日：1997-12-16

申请号：US539380

申请日：1995-10-05

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： Y02E10/50

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5654560A

公开(公告)日：1997-08-05

申请号：US475096

申请日：1995-06-07

申请人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

发明人： Toshiaki Nishizawa ,  Akira Kuroyanagi ,  Tsuyoshi Yamamoto ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L29/74

CPC分类号： H01L29/66712 ,  H01L27/0248 ,  H01L29/7811 ,  H01L29/7815 ,  Y10S148/126

摘要： A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.

摘要翻译： 一种具有电流检测功能的功率半导体器件，包括检测部件，该检测部件包括比主电流部件更好的达到耐受电压能力的元件。 功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。 设备的一个区域作为检测部分，另一个作为主要的当前部分。 检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。 低密度层的表面分别载有第二导电类型的主要和次要的阱区。 主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。 通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。 这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

公开(公告)号：US07586151B2

公开(公告)日：2009-09-08

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。 栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US20070200138A1

公开(公告)日：2007-08-30

申请号：US11709272

申请日：2007-02-22

申请人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

发明人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

IPC分类号： H01L29/74

CPC分类号： H01L27/0611 ,  H01L29/7395 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

摘要翻译： 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

公开(公告)号：US6133587A

公开(公告)日：2000-10-17

申请号：US23280

申请日：1998-02-13

申请人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

发明人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/0696

摘要： A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

摘要翻译： n型源极区5形成在半导体衬底4的p型碳化硅半导体层3的表层部分的预定区域上。低电阻p型碳化硅区6形成在 在p型碳化硅半导体层3中的表层部分的预定区域。沟槽7形成在n +型源极区域5中的预定区域中，沟槽7通过n +型源极区域5，并且 p型碳化硅半导体层3，到达n型碳化硅半导体层2.沟槽7具有垂直于半导体衬底4的表面的侧壁7a和平行于半导体衬底的表面的底侧7b 由沟槽7的侧壁7a包围的六边形区域是岛状半导体区域12.通过在侧壁7a上形成栅极绝缘层，形成高可靠性栅极绝缘膜8， 岛半导体区域12。