公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US6015737A

公开(公告)日：2000-01-18

申请号：US515176

申请日：1995-08-15

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/4236

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： 垂直型功率MOSFET可显着降低每个区域的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US5776812A

公开(公告)日：1998-07-07

申请号：US413410

申请日：1995-03-30

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuchi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/045 ,  H01L29/7813 ,  H01L29/4236

摘要： A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer. After the double diffusion, a gate electrode is formed through a gate oxide film and a source electrode and a drain electrode are formed.

摘要翻译： 一种MOSFET的制造方法，其具有在槽的侧面上的通道部分，其不允许将缺陷或污染物引入通道部分中并且可以使槽的形状均匀。 在n +型半导体衬底的主表面上形成具有低杂质浓度的n型外延层。 该表面被指定为主表面，并且化学干蚀刻被施加到该主表面的指定区域。 包括通过化学干蚀刻生成的表面的区域被选择性地氧化以形成具有特定厚度的选择性氧化膜。 在该过程之后，p型和n型杂质从主表面双重扩散以限定通道的长度并形成基层和源层。 此外，n +型半导体衬底被指定为漏极层。 在双扩散之后，通过栅极氧化膜形成栅电极，形成源电极和漏电极。

公开(公告)号：US5698880A

公开(公告)日：1997-12-16

申请号：US539380

申请日：1995-10-05

申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： Y02E10/50

摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

公开(公告)号：US5696396A

公开(公告)日：1997-12-09

申请号：US734132

申请日：1996-10-21

申请人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

发明人： Norihito Tokura ,  Kunihiko Hara ,  Takeshi Miyajima

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76 ,  H01L31/0312 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7802

摘要： A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.- silicon layer to be negligibly small as compared with the current flowing from the source terminal through the source electrode to the n.sup.+ source region, the channel region and the n.sup.- silicon layer.

摘要翻译： 可以获得只能通过栅极电压控制流过器件的交流电流的垂直MOSFET。 在n +硅层上形成n-硅层。 在n-硅层内形成p体区域。 在p体区内形成n +源区。 在基板顶部形成仅与源极区域接触的源极电极和仅与p体区域接触的基极电极。 源电极和基极通过外部的电阻彼此连接。 在沟道区域上通过栅极氧化膜（绝缘膜）形成栅电极。 当上述半导体器件处于反向偏压传导时，通过将从源极端子流过电流的电流设置到基极，p体区域和n-硅层，从而仅通过栅极电压来控制励磁电流 与源极端子通过源极电极流到n +源极区域，沟道区域和n-硅层的电流相比，可以忽略不计。

公开(公告)号：US5504360A

公开(公告)日：1996-04-02

申请号：US293421

申请日：1994-08-22

申请人： Norihito Tokura ,  Kunihiko Hara

发明人： Norihito Tokura ,  Kunihiko Hara

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/7802 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/41766

摘要： A vertical type semiconductor device is provided with an improved construction which greatly decreases the on-resistance without impairing the breakdown voltage thereof. In the fundamental DMOS cells that control a current to constitute the vertical semiconductor device, through-hole cells are arranged along the sides of a cell having a channel. The through-hole cell includes a through-hole extending from the surface of an n.sup.- -type drift region toward an n.sup.+ -type drain region, and also includes an n.sup.+ -type through-hole region that is formed by diffusing impurities from the inner wall of the through-hole which is continuous with the n.sup.+ -type drain region. A breakdown voltage of the element is maintained by the n.sup.- -type drift region between a p-type well region and the n.sup.+ -type through-hole region or the n.sup.+ -type drain region. Given the unique arrangement of the through-hole cells, the JFET resistance component becomes negligibly small between the DMOS cells neighboring along the sides of the cells despite the fact that the cells are finely formed, and a small on-resistance is exhibited.

摘要翻译： 垂直型半导体器件具有改进的结构，其大大降低导通电阻而不损害其击穿电压。 在控制电流以构成垂直半导体器件的基本DMOS单元中，沿着具有沟道的单元的侧面布置有通孔单元。 通孔单元包括从n型漂移区域的表面向n +型漏极区域延伸的通孔，还包括通过从内部扩散杂质形成的n +型通孔区域 与n +型漏极区连续的通孔的壁。 元件的击穿电压由p型阱区域和n +型通孔区域或n +型漏极区域之间的n型漂移区域维持。 鉴于通孔单元的独特布置，尽管细胞形成细小，但是出现小的导通电阻，但是JFET电阻分量在沿着单元侧面相邻的DMOS单元之间变得可以忽略不计。

公开(公告)号：US4962411A

公开(公告)日：1990-10-09

申请号：US307177

申请日：1989-02-03

申请人： Norihito Tokura ,  Hironari Kuno ,  Hiroyasu Ito ,  Hirohiko Saito ,  Kunihiko Hara

发明人： Norihito Tokura ,  Hironari Kuno ,  Hiroyasu Ito ,  Hirohiko Saito ,  Kunihiko Hara

IPC分类号： H01L27/02 ,  H01L29/78

CPC分类号： H01L29/7815 ,  H01L27/0248 ,  H01L29/423

摘要： A semiconductor device with a current detecting function in which in place of an external resistor for detecting an operation current such as drain current or collector current of a device such as an FET or bipolar transistor, a probe electrode is formed in proximity to the device depletion layer to connect therethrough with the device channel to generate a probe voltage corresponding to the operation current.

摘要翻译： 具有电流检测功能的半导体器件，其中代替用于检测诸如FET或双极晶体管的器件的漏极电流或集电极电流等工作电流的外部电阻器，形成探针电极附近的器件耗尽 层与器件通道连接以产生对应于工作电流的探针电压。

公开(公告)号：US5460985A

公开(公告)日：1995-10-24

申请号：US30338

申请日：1993-03-25

申请人： Norihito Tokura ,  Shigeki Takahashi

发明人： Norihito Tokura ,  Shigeki Takahashi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8232

CPC分类号： H01L29/0696 ,  H01L21/28167 ,  H01L29/045 ,  H01L29/7813 ,  H01L21/28211 ,  H01L29/4236 ,  Y10S148/116 ,  Y10S148/126

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： PCT No.PCT / JP92 / 00929 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT提交1992年7月22日PCT公布。 公开号WO93 / 03502 日期：1993年2月18日。垂直型功率MOSFET显着降低了其面积的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US08854033B2

公开(公告)日：2014-10-07

申请号：US13150764

申请日：2011-06-01

申请人： Satoshi Shiraki ,  Norihito Tokura ,  Shigeki Takahashi ,  Masahiro Yamamoto ,  Akira Yamada ,  Hiroyasu Kudo ,  Youichi Ashida ,  Akio Nakagawa

发明人： Satoshi Shiraki ,  Norihito Tokura ,  Shigeki Takahashi ,  Masahiro Yamamoto ,  Akira Yamada ,  Hiroyasu Kudo ,  Youichi Ashida ,  Akio Nakagawa

IPC分类号： G01R1/20

CPC分类号： H01L27/1203 ,  G01R19/0092 ,  H01L21/76283 ,  H01L23/585 ,  H01L29/0696 ,  H01L29/405 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.

摘要翻译： 具有横向半导体元件的半导体器件包括半导体衬底，衬底上的第一电极，衬底上的第二电极和位于衬底中的隔离结构，以将衬底分成第一岛和与第一岛电绝缘的第二岛 第一个岛屿。 横向半导体元件包括位于第一岛中的主单元和位于第二岛中的感测单元。 主电池使得第一电流在第一电极和第二电极之间流动，使得第一电流沿着基板的表面在横向方向上流动。 通过检测流过感测单元的第二电流来检测第一电流。

公开(公告)号：US20140048911A1

公开(公告)日：2014-02-20

申请号：US14113419

申请日：2012-05-10

申请人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

发明人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

IPC分类号： H01L29/06

CPC分类号： H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/861

摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.

摘要翻译： 横向半导体器件包括半导体层，绝缘层和电阻场板。 半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。 绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。 电阻场板形成在绝缘层的表面上。 在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。 电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。