利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

73 条记录 (耗时 0.023 秒)

    Semiconductor device contact structures and methods for making the same
    1.
    发明授权
    Semiconductor device contact structures and methods for making the same 有权
    半导体器件接触结构及其制造方法

    公开(公告)号：US08518819B2

    公开(公告)日：2013-08-27

    申请号：US13049049

    申请日：2011-03-16

    申请人： Shih Chieh Chang ,  Chih-Chung Chang ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shih Chieh Chang ,  Chih-Chung Chang ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/53266 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

    摘要翻译： 半导体接触结构和方法提供延伸穿过电介质材料并提供与包括硅化物材料和非硅化物材料（例如掺杂硅）的多个不同下层材料的接触的接触结构。 接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。 下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。 复合层可以由钛形成。 在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。 诸如钨或铜的导电插塞材料填充接触开口。

    Via/contact and damascene structures and manufacturing methods thereof
    4.
    发明授权
    Via/contact and damascene structures and manufacturing methods thereof 有权
    通孔/接触和镶嵌结构及其制造方法

    公开(公告)号：US08247322B2

    公开(公告)日：2012-08-21

    申请号：US11680981

    申请日：2007-03-01

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.

    摘要翻译： 形成半导体结构的方法包括在衬底上形成电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

    Via/contact and damascene structures
    8.
    发明授权
    Via/contact and damascene structures 有权
    通过/接触和镶嵌结构

    公开(公告)号：US08531036B2

    公开(公告)日：2013-09-10

    申请号：US13563495

    申请日：2012-07-31

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.

    摘要翻译： 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。

    VIA/CONTACT AND DAMASCENE STRUCTURES
    9.
    发明申请
    VIA/CONTACT AND DAMASCENE STRUCTURES 有权
    威盛/联系人和大马士革结构

    公开(公告)号：US20120292768A1

    公开(公告)日：2012-11-22

    申请号：US13563495

    申请日：2012-07-31

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76831 ,  H01L21/7684

    摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.

    摘要翻译： 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。

    Barrier layer for semiconductor interconnect structure
    10.
    发明申请
    Barrier layer for semiconductor interconnect structure 审中-公开
    半导体互连结构的阻挡层

    公开(公告)号：US20070257366A1

    公开(公告)日：2007-11-08

    申请号：US11416945

    申请日：2006-05-03

    申请人： Yu-Sheng Wang ,  Jung-Chih Tsao ,  Kei-Wei Chen ,  Shih-Chieh Chang ,  Ying-Lang Wang

    发明人： Yu-Sheng Wang ,  Jung-Chih Tsao ,  Kei-Wei Chen ,  Shih-Chieh Chang ,  Ying-Lang Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L21/76844 ,  H01L21/76865

    摘要： A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.

    摘要翻译： 一种具有电互连的半导体器件的制造方法。 该方法产生在互连导体和形成有互连凹槽的电介质材料之间具有改进的阻挡层。 在具有至少一个接触区域的晶片衬底的顶部上形成电介质层。 通过形成互连凹槽然后沉积氮化钽的主阻挡层并对其进行再溅射操作来制造用于维护接触区域的互连。 然后沉积钽薄膜层并重新溅射。 在该操作之后，形成种子层，然后使用导体来填充互连凹槽。 使晶片的表面平整化，以便进一步制造可以完成该工艺。