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    Process for producing polyester sheet and film
    2.
    发明授权
    Process for producing polyester sheet and film 失效
    生产聚酯片和薄膜的方法

    公开(公告)号：US06797225B2

    公开(公告)日：2004-09-28

    申请号：US10069075

    申请日：2002-02-21

    申请人： Norio Takagi ,  Shozo Nitta ,  Yo Goto

    发明人： Norio Takagi ,  Shozo Nitta ,  Yo Goto

    IPC分类号： B29C4126

    CPC分类号： B29C47/8845 ,  B29C47/0021 ,  B29C47/0057 ,  B29C47/8865 ,  B29C47/887 ,  B29K2067/00 ,  B29K2105/256 ,  B29L2007/002

    摘要： A process for producing a polyester sheet by dropping a molten polyester sheet extruded from an orifice-form nozzle on a cooling roll having the grooves of a large number of micro-cracks formed on the surface, closely adhering it to the cooling roll and solidifying it on the cooling roll, wherein the surface temperature (T, ° C.) of the molten polyester sheet 10 mm below the orifice-form nozzle is maintained at a temperature which satisfies the following expression (1): (Tc+20)° C.≦T≦(Tm+40)° C.  (1) wherein Tc and Tm are the falling temperature crystallization temperature (° C.) and melting point (° C.) of the polyester, respectively and T is as defined hereinabove, and the surface temperature of the cooling roll when it contacts the molten polyester sheet is controlled to a range of 5 to 100° C. to continuously form the polyester sheet while preventing the adhesion of a sublimate from the molten polyester to the inside of the groove of each micro-crack of the cooling roll.

    摘要翻译： 通过将从孔形喷嘴挤出的熔融聚酯片材滴下到具有形成在表面上的大量微裂纹的槽的冷却辊上，将其紧密地附着在冷却辊上并固化，从而生产聚酯片材的方法 在冷却辊上，在孔形喷嘴下方10mm的熔融聚酯片的表面温度（T，℃）保持在满足以下表达式（1）的温度：其中Tc和Tm是下降温度 聚酯的结晶温度（℃）和熔点（℃）分别为T，如上所述，冷却辊与熔融聚酯片接触时的表面温度控制在5〜 100℃，以连续地形成聚酯片材，同时防止升华物从熔融聚酯粘附到冷却辊的每个微裂纹的槽的内部。

    Bias current supplying circuit
    3.
    发明授权
    Bias current supplying circuit 失效
    偏置电流供应电路

    公开(公告)号：US5397935A

    公开(公告)日：1995-03-14

    申请号：US33890

    申请日：1993-03-18

    申请人： Shozo Nitta

    发明人： Shozo Nitta

    IPC分类号： H03K19/00 ,  G05F3/22 ,  H03F3/72 ,  H03K19/086 ,  H03K5/01 ,  H03K5/153 ,  H03K17/687

    CPC分类号： G05F3/22 ,  H03F3/72

    摘要： A bias current supplying circuit having: a differential amplifier for amplifying a difference between potentials at first and second nodes and outputting the amplified difference voltage from a third node, the first node being connected to an output terminal of a bias voltage source for outputting a bias voltage, and the second node being connected to an output terminal from which a bias current is supplied to an external circuit; a negative feedback loop circuit for changing the potential at the second node in accordance with the potential at the third node of the differential amplifier; and a potential dropping circuit connected to the second node for dropping the potential at the second node in response to an external input of a control signal and intercepting a supply of the bias current to the external circuit.

    摘要翻译： 一种偏置电流供应电路，具有：差分放大器，用于放大第一和第二节点处的电位差，并从第三节点输出放大的差分电压，第一节点连接到偏置电压源的输出端，用于输出偏置 电压，并且所述第二节点连接到输出端子，偏置电流从所述输出端子提供给外部电路; 用于根据差分放大器的第三节点处的电位改变第二节点处的电位的负反馈回路电路; 以及连接到第二节点的电位下降电路，用于响应于控制信号的外部输入而丢弃第二节点处的电位，并截断向外部电路的偏置电流的供应。

    Timing generating device
    5.
    发明授权
    Timing generating device 失效
    定时发生装置

    公开(公告)号：US5627795A

    公开(公告)日：1997-05-06

    申请号：US418289

    申请日：1995-04-07

    申请人： Shozo Nitta

    发明人： Shozo Nitta

    IPC分类号： H03K5/135 ,  G06F1/06 ,  G11C29/14 ,  G11C8/00

    CPC分类号： G06F1/06 ,  G11C29/14

    摘要： The timings can be generated in synchronism with master clocks, so that it is possible to obtain the timing generating device of synchronous circuit, which is effectively applicable to a large scale integrated circuit, while facilitating the test thereof. Addresses A [0, m-1] are given to the register 1 in synchronism with the input pulses CLK; delay data D [0, n-1] are read from the memory device 3 on the basis of the outputs of the register 1; the delayed data are stored in the registers 4-1 to 4-k independently on the basis of the distributive pulses CK1 to CKk applied by the pulse distributing circuit 2 for distributing the input pulse CLK to a plurality of routes in sequence; the data signals S1i to Ski obtained by the registers 4-1 to 4-k are given to the delay circuits 6-1 to 6-k through the DA converters 5-1 to 5-k to control the delay times in such a way that the distributive pulses CK1 to CKk can be controllably delayed by the delay circuits 6-1 to 6-k; and the obtained delay pulses CK1X to CKkX are outputted through the OR gate 7 as a continuous pulse train.

    摘要翻译： 可以与主时钟同步地产生定时，从而可以获得同步电路的定时发生装置，其有效地适用于大规模集成电路，同时便于其测试。 地址A [0，m-1]与输入脉冲CLK同步地被提供给寄存器1; 基于寄存器1的输出从存储器件3读取延迟数据D [0，n-1] 基于由脉冲分配电路2施加的用于将输入脉冲CLK顺序分配到多个路由的分配脉冲CK1至CKk独立地将延迟数据存储在寄存器4-1至4-k中; 由寄存器4-1至4-k获得的数据信号S1i至Ski通过DA转换器5-1至5-k被提供给延迟电路6-1至6-k，从而以这种方式控制延迟时间 分配脉冲CK1至CKk可被延迟电路6-1至6-k可控地延迟; 所获得的延迟脉冲CK1X至CKkX作为连续脉冲串通过或门7输出。

    Level converter for converting ECL-level signal voltage to TTL-level signal voltage
    6.
    发明授权
    Level converter for converting ECL-level signal voltage to TTL-level signal voltage 失效
    电平转换器，用于将ECL电平信号电压转换为TTL电平信号电压

    公开(公告)号：US5081376A

    公开(公告)日：1992-01-14

    申请号：US674786

    申请日：1991-03-25

    申请人： Shozo Nitta ,  Yasuhiro Sugimoto

    发明人： Shozo Nitta ,  Yasuhiro Sugimoto

    IPC分类号： H03K5/02 ,  H03K19/018

    CPC分类号： H03K19/01812

    摘要： According to this invention, a level converter has a pair of differential transistors operated at a negative voltage in accordance with an ECL-level input signal, and first and second output nodes are arranged between a collector of one transistor of the pair of differential transistors and a positive power source voltage. A level-converting resistor for converting an ECL-level signal to a positive level signal is inserted between the first output node and the second output node so as to output the positive level signal in accordance with an ECL-level input signal to the first output node. The emitter-collector path of a bipolar transistor is inserted between the second output node and the positive power source voltage. A clamp potential for controlling saturation of transistors constituting a TTL circuit connected to an output of the transistor is generated by a constant potential applied to the base of the transistor.

    Differential RS latch circuit
    7.
    发明授权
    Differential RS latch circuit 失效
    差分RS锁存电路

    公开(公告)号：US5604456A

    公开(公告)日：1997-02-18

    申请号：US576370

    申请日：1995-12-21

    申请人： Shozo Nitta

    发明人： Shozo Nitta

    IPC分类号： H03K3/286 ,  H03K3/2885 ,  H03K3/037 ,  H03K3/26

    CPC分类号： H03K3/2885

    摘要： A differential RS latch circuit has a series structure wherein a first differential transistor pair, a second differential transistor pair and a third differential transistor pair are connected in three stages, and jointly function as one current switch. A first diode serving as a first level shift element is provided in a first current path between a power source node and a grounding node, and second and third diodes serving as second and third level shift elements are provided in a second current path between the power source node and the grounding node. The number of elements provided in the first current path is equal to that of elements provided in the second current path. As a result, the first and second current paths are equal to each other in response speed to a signal, and thus an hazard is prevented from occurring even at the time of the switching operation between the first and second current paths.

    摘要翻译： 差分RS锁存电路具有串联结构，其中第一差分晶体管对，第二差分晶体管对和第三差分晶体管对三级连接，并且共同作为一个电流开关。 用作第一电平移位元件的第一二极管设置在电源节点和接地节点之间的第一电流路径中，并且用作第二和第三电平移位元件的第二和第三二极管设置在电源 源节点和接地节点。 在第一电流路径中提供的元件的数量等于在第二电流路径中提供的元件的数量。 结果，第一和第二电流路径相对于信号的响应速度彼此相等，因此即使在第一和第二电流路径之间的切换操作时也防止发生危险。