公开(公告)号：US5081376A

公开(公告)日：1992-01-14

申请号：US674786

申请日：1991-03-25

申请人： Shozo Nitta ,  Yasuhiro Sugimoto

发明人： Shozo Nitta ,  Yasuhiro Sugimoto

IPC分类号： H03K5/02 ,  H03K19/018

CPC分类号： H03K19/01812

摘要： According to this invention, a level converter has a pair of differential transistors operated at a negative voltage in accordance with an ECL-level input signal, and first and second output nodes are arranged between a collector of one transistor of the pair of differential transistors and a positive power source voltage. A level-converting resistor for converting an ECL-level signal to a positive level signal is inserted between the first output node and the second output node so as to output the positive level signal in accordance with an ECL-level input signal to the first output node. The emitter-collector path of a bipolar transistor is inserted between the second output node and the positive power source voltage. A clamp potential for controlling saturation of transistors constituting a TTL circuit connected to an output of the transistor is generated by a constant potential applied to the base of the transistor.

公开(公告)号：US07889509B2

公开(公告)日：2011-02-15

申请号：US11513039

申请日：2006-08-31

申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

IPC分类号： H05K7/00

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A circuit board (10, 10″, 10′″) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

摘要翻译： 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器表面（103）的陶瓷电容器（101,101'，101“，101”，101“”，101“”，101“”“）， 其中第一内部电极层（141）和第二内部电极层（142）交替层叠有介于其间的陶瓷介电层（105），并且具有多个电容器功能单元（107,108），其电独立于 相互之间的陶瓷电容器（101,101'，101“，101”，101“，101”，101“”101“”）被埋在板芯11中， （12）和主电容器表面（102）指向相同的方向; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

公开(公告)号：US07339260B2

公开(公告)日：2008-03-04

申请号：US10927134

申请日：2004-08-27

申请人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

发明人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

IPC分类号： H01L23/12 ,  H01L23/02 ,  H05K3/46 ,  H05K1/02 ,  H01H29/40

CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole as defined herein; a signal through-hole conductor as defined herein; a first path end pad as defined herein; a second path end pad as defined herein; a shield through-hole as defined herein; and a shield through-hole conductor as defined herein; wherein: a signal transmission path is formed as defined herein; at least one of said conductor layers is disposed on each of said first and second main surface sides; said surface conductor on said first main surface side and said conductor line form a strip line, a microstrip line, or a coplanar waveguide with constant characteristic impedance Z0; an inner surface of said shield through-hole is covered with said shield through-hole conductor; and an interaxis distance between said signal through-hole conductor and said shield through-hole conductor is adjusted as defined herein.

摘要翻译： 一种布线板，包括：板芯，具有第一主表面和第二主表面; 包括导体线的导体层; 电介质层与所述导体层交替地层叠在所述第一和第二主表面中的至少一个上; 通孔导体; 如本文所定义的信号通孔; 如本文所定义的信号通孔导体; 如本文所定义的第一路径端垫; 如本文所定义的第二路径端垫; 如本文所定义的屏蔽通孔; 和如本文所定义的屏蔽通孔导体; 其中：如本文所定义的形成信号传输路径; 所述导体层中的至少一个设置在所述第一和第二主表面侧的每一个上; 所述第一主表面侧的所述表面导体和所述导体线形成具有恒定特性阻抗Z 0的带状线，微带线或共面波导; 所述屏蔽通孔的内表面被所述屏蔽通孔导体覆盖; 并且如本文所定义的那样调整所述信号通孔导体和所述屏蔽通孔导体之间的间隔距离。

公开(公告)号：US20070137591A1

公开(公告)日：2007-06-21

申请号：US10591304

申请日：2005-09-20

申请人： Yasuhiro Sugimoto ,  Hiroaki Kojima ,  Kazuhito Takemura ,  Katsuhiro Nakagawa

发明人： Yasuhiro Sugimoto ,  Hiroaki Kojima ,  Kazuhito Takemura ,  Katsuhiro Nakagawa

IPC分类号： F01P1/02 ,  F02B43/00

CPC分类号： F02D29/06 ,  F01P5/06 ,  F01P9/02 ,  F02B43/00 ,  F02B63/04 ,  F02B63/044 ,  F02D19/022 ,  F02D19/027 ,  F02D19/0615 ,  F02D19/0647 ,  F02D19/0676 ,  F02M21/0224 ,  F02M21/0287 ,  F02M21/029 ,  F02M21/047 ,  F02M21/06 ,  Y02T10/32 ,  Y02T10/36

摘要： An engine operated generator is provided with an engine, a generator driven by the engine, and a power control unit for controlling the power generated by the generator. A fuel gas stored in fuel bottles set in a case for the engine operated generator, is supplied to the engine though a fuel pressure regulator. The fuel bottles and the fuel pressure regulator are disposed adjacent to the power control unit to enable heat exchange with the power control unit provided with an inverter. Thus, heat is mutually utilized between the power control unit and at least one of the fuel bottles as fuel receptacles and the fuel pressure regulator.

摘要翻译： 发动机运转的发电机配备有发动机，由发动机驱动的发电机和用于控制发电机产生的动力的功率控制单元。 存储在设置在用于发动机操作的发电机的壳体中的燃料瓶中的燃料气体通过燃料压力调节器供应到发动机。 燃料瓶和燃料压力调节器设置在与功率控制单元相邻的位置，以实现与设置有逆变器的功率控制单元的热交换。 因此，在功率控制单元和作为燃料容器和燃料压力调节器的燃料瓶中的至少一个之间相互利用热量。

公开(公告)号：US06979890B2

公开(公告)日：2005-12-27

申请号：US11127192

申请日：2005-05-12

申请人： Rokuro Kambe ,  Tetsuya Kasiwagi ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

发明人： Rokuro Kambe ,  Tetsuya Kasiwagi ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

IPC分类号： H01F5/00 ,  H01L23/02 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/46

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

摘要： An intermediate substrate is provided which reduces the effect of the difference in the coefficients of linear expansion between the terminals of the substrate and those of a semiconductor integrated circuit device, and which thus lowers the likelihood of disconnection due to thermal stress. The intermediate substrate, which is a planar member made of a polymeric material, includes a substrate core including a main core body having formed therein a sub-core compartment, and a ceramic sub-core section accommodated in the compartment. A first terminal array on the first principal surface side includes two types of terminals, functioning either as power source terminals or ground terminals, and a signal terminal. The array occupies an area entirely included within an orthogonally projected region of the sub-core section projected onto a reference plane parallel to the planar surface of the substrate core.

摘要翻译： 提供了一种中间衬底，其减小了衬底的端子与半导体集成电路器件的端子之间的线性膨胀系数的差异的影响，从而降低了由于热应力引起的断开的可能性。 作为由聚合物材料制成的平面构件的中间基板包括：基材芯，其包括形成有副芯隔室的主芯体和容纳在隔室中的陶瓷副芯部。 第一主表面侧的第一端子阵列包括用作电源端子或接地端子的两种类型的端子和信号端子。 阵列占据完全包括在子芯部分的正交投影区域内的区域，该区域投影到平行于衬底芯的平面表面的参考平面上。

公开(公告)号：US20050207091A1

公开(公告)日：2005-09-22

申请号：US11126157

申请日：2005-05-11

申请人： Rokuro Kambe ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

发明人： Rokuro Kambe ,  Yukihiro Kimura ,  Yasuhiro Sugimoto ,  Kazuhiro Suzuki

IPC分类号： H01L23/12 ,  H01G4/228 ,  H01L23/498 ,  H01L23/50 ,  H01L27/01 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC分类号： H05K1/0231 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/50 ,  H01L27/016 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2224/05599

摘要： An intermediate substrate includes a substrate core formed by a main core body portion constructed of a sheet of polymer material and having a subsidiary core accommodation portion formed therein. A ceramic subsidiary core portion, which is constructed of a ceramic sheet, is accommodated in the subsidiary core accommodation portion and is of a thickness matching that of the main core body portion. A thin film capacitor is formed on a first main surface side of a plate-like base of the core portion and includes first and second thin film electrodes separated from each other by a thin film dielectric layer so as to provide direct current isolation between the electrodes. First and second direct current isolated terminals of a first terminal array are electrically connected to the first and second thin film electrodes.

摘要翻译： 中间基板包括由主体芯体部分形成的基体芯部，所述主芯体部分由聚合物材料片构成并且具有形成在其中的副芯部容纳部分。 由陶瓷片构成的陶瓷副芯部被容纳在副芯容纳部中，其厚度与主芯体部的厚度一致。 在芯部的板状基体的第一主面侧形成薄膜电容器，并且包括通过薄膜电介质层彼此分离的第一和第二薄膜电极，以在电极之间提供直流隔离 。 第一端子阵列的第一和第二直流隔离端子电连接到第一和第二薄膜电极。

公开(公告)号：US5278491A

公开(公告)日：1994-01-11

申请号：US865663

申请日：1992-04-07

申请人： Shouzou Nitta ,  Yasuhiro Sugimoto

发明人： Shouzou Nitta ,  Yasuhiro Sugimoto

IPC分类号： G05F3/30 ,  G05F3/26

CPC分类号： G05F3/30

摘要： This invention discloses a constant voltage circuit including a bandgap circuit connected between a ground voltage and a source voltage, a transistor, the collector of which is connected to the collector of a negative feedback transistor for supplying a voltage of a base-emitter path to the other terminal of a resistor having one terminal connected to an output terminal of the bandgap circuit, and the base of which is connected to a voltage source free from variations in source voltage, and a resistor connected between the emitter of the transistor and the source voltage.

摘要翻译： 本发明公开了一种包括连接在接地电压和源电压之间的带隙电路的恒压电路，晶体管，其集电极连接到负反馈晶体管的集电极，用于将基极 - 发射极路径的电压提供给 电阻器的另一个端子，其一个端子连接到带隙电路的输出端子，并且其基极连接到没有源极电压变化的电压源，以及连接在晶体管的发射极和源极电压之间的电阻器 。

公开(公告)号：US4912394A

公开(公告)日：1990-03-27

申请号：US355610

申请日：1989-05-23

申请人： Yasuhiro Sugimoto ,  Hiromi Mafune

发明人： Yasuhiro Sugimoto ,  Hiromi Mafune

IPC分类号： H03H7/24

CPC分类号： H03H7/24

摘要： An attenuator circuit is provided which comprises an input node, a first resistor connected at one terminal to a reference potential, a second resistor connected to the other terminal of the first resistor, a first output node which is a connection node of the first resistor and the second resistor, a third resistor connected in parallel with the series circuit of the first and second resistors and being of such a type that a resultant resistive value of the first, second and third resistors is equal to a resistive value of the first resistor, a fourth resistor connected at one terminal to a connection node of the second and third resistors and having a resistive value substantially equal to that of the second resistor, and at least one combination resistor of a ladder configuration connected between the other terminal of the fourth resistor and the input node and having a third output node as a junction of its series circuit portion.

摘要翻译： 提供了一种衰减器电路，其包括输入节点，在一个端子处连接到参考电位的第一电阻器，连接到第一电阻器的另一端子的第二电阻器，作为第一电阻器的连接节点的第一输出节点和 第二电阻器，与第一和第二电阻器的串联电路并联连接的第三电阻器，并且是第一，第二和第三电阻器的合成电阻值等于第一电阻器的电阻值的类型， 在一个端子处连接到第二和第三电阻器的连接节点并且具有基本上等于第二电阻器的电阻值的电阻值的第四电阻器，以及连接在第四电阻器的另一个端子之间的梯形配置的至少一个组合电阻器 和输入节点，并具有作为其串联电路部分的结点的第三输出节点。

公开(公告)号：US4839609A

公开(公告)日：1989-06-13

申请号：US173657

申请日：1988-03-25

申请人： Hiroyuki Hara ,  Yasuhiro Sugimoto

发明人： Hiroyuki Hara ,  Yasuhiro Sugimoto

IPC分类号： H03F1/22 ,  H03F3/45

CPC分类号： H03F3/45076

摘要： To provide a high-speed wide-dynamic range differential amplifier, the amplifier comprises first and second FETs having source terminals connected to each other and a constant current source connected between the sources and ground; third and fourth bipolar transistors complementary to the first and second FETs, having base terminals connected to a first bias voltage in common and emitter terminals connected to the drains of the first and second FETs and a supply voltage via resistors, respectively; and a current mirror circuit composed of fifth and sixth FETs of the same conductive type as the first and second FETs.

公开(公告)号：US4798980A

公开(公告)日：1989-01-17

申请号：US49141

申请日：1987-05-13

申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

IPC分类号： G06F7/53 ,  G06F7/44 ,  G06F7/52 ,  G06F7/533 ,  H03K19/21 ,  H03K19/017 ,  H03K19/094

CPC分类号： G06F7/5332

摘要： A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

摘要翻译： 一种展位的算法转换电路，具有由输入信号QX和Q2X控制的第一和第二开关，并且接收位于被乘数X的i数位顺序的逻辑电平的信号Xi和位于该位置的逻辑电平的信号Xi-1 被乘数X的i-1位数。第一和第二开关的输出通过由信号QX和Q2X控制的第一和第二转换器连接在一起并接地，第一和第二晶体管与第一和第二开关反向关系 开关电路。 第一和第二开关电路的公共输出被输入到异或电路，该异或电路接收额外的逻辑1或逻辑0输入信号以产生布斯的转换输出。 所产生的电路元件和门的数量提供了简化的高速和小电路，用于生产Booth的转换。