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    GLITCHLESS CLOCK SWITCHING THAT HANDLES STOPPED CLOCKS
    1.
    发明申请
    GLITCHLESS CLOCK SWITCHING THAT HANDLES STOPPED CLOCKS 有权
    无柄时钟切换手柄停止时钟

    公开(公告)号：US20140118033A1

    公开(公告)日：2014-05-01

    申请号：US13662165

    申请日：2012-10-26

    Applicant: SILICON LABORATORIES INC.

    Inventor： William J. Anker ,  Srisai R. Seethamraju

    IPC: H03L7/00

    CPC classification number: G06F1/04 ,  H03K5/1252

    Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

    Abstract translation: 集成电路接收第一和第二时钟信号以及选择时钟信号之一的选择信号。 无毛刺切换电路根据选择信号选择第一和第二时钟中的哪一个提供输出时钟信号。 耦合到无毛刺切换电路的复位电路响应于选择信号的转变方向，响应于转换的第一方向产生第一复位信号，并且响应于转换的第二方向产生第二复位信号 。 复位脉冲分别提供给无毛切换电路中的第一和第二路径，以便在输入时钟之一不存在的情况下复位由第一和第二路径形成的状态机。

    Jitter self-test using timestamps
    2.
    发明授权
    Jitter self-test using timestamps 有权

    公开(公告)号：US11228403B2

    公开(公告)日：2022-01-18

    申请号：US16707401

    申请日：2019-12-09

    Applicant: Silicon Laboratories Inc.

    Inventor： Raghunandan K. Ranganathan ,  Kannanthodath V. Jayakumar ,  Srisai R. Seethamraju

    IPC: H04L1/20 ,  G01R31/30 ,  G01R29/26 ,  G01R31/317

    Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

    Spur and quantization noise cancellation for PLLS with non-linear phase detection
    3.
    发明授权
    Spur and quantization noise cancellation for PLLS with non-linear phase detection 有权

    公开(公告)号：US11038521B1

    公开(公告)日：2021-06-15

    申请号：US16805336

    申请日：2020-02-28

    Applicant: Silicon Laboratories Inc.

    Inventor： Aslamali A. Rafi ,  Srisai R. Seethamraju ,  Russell Croman ,  James D. Barnette

    IPC: H03M3/00 ,  H03L7/093 ,  H03L7/197

    Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

    JITTER SELF-TEST USING TIMESTAMPS
    5.
    发明申请
    JITTER SELF-TEST USING TIMESTAMPS 有权

    公开(公告)号：US20210176020A1

    公开(公告)日：2021-06-10

    申请号：US16707401

    申请日：2019-12-09

    Applicant: Silicon Laboratories Inc.

    Inventor： Raghunandan K. Ranganathan ,  Kannanthodath V. Jayakumar ,  Srisai R. Seethamraju

    IPC: H04L1/20 ,  G01R31/30 ,  G01R31/317 ,  G01R29/26

    Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

    Glitchless clock switching that handles stopped clocks
    10.
    发明授权
    Glitchless clock switching that handles stopped clocks 有权
    无时钟切换，可处理停止的时钟

    公开(公告)号：US09207704B2

    公开(公告)日：2015-12-08

    申请号：US13662165

    申请日：2012-10-26

    Applicant: Silicon Laboratories Inc.

    Inventor： William J. Anker ,  Srisai R. Seethamraju

    IPC: G06F1/08 ,  G06F1/04 ,  H03K5/1252

    CPC classification number: G06F1/04 ,  H03K5/1252

    Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

    Abstract translation: 集成电路接收第一和第二时钟信号以及选择时钟信号之一的选择信号。 无毛刺切换电路根据选择信号选择第一和第二时钟中的哪一个提供输出时钟信号。 耦合到无毛刺切换电路的复位电路响应于选择信号的转变方向，响应于转换的第一方向产生第一复位信号，并且响应于转换的第二方向产生第二复位信号 。 复位脉冲分别提供给无毛切换电路中的第一和第二路径，以便在输入时钟之一不存在的情况下复位由第一和第二路径形成的状态机。

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