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    TIME-TO-DIGITAL CONVERTER BASED ON A VOLTAGE CONTROLLED OSCILLATOR
    3.
    发明申请
    TIME-TO-DIGITAL CONVERTER BASED ON A VOLTAGE CONTROLLED OSCILLATOR 有权
    基于电压控制振荡器的数字时钟转换器

    公开(公告)号：US20150145570A1

    公开(公告)日：2015-05-28

    申请号：US14448482

    申请日：2014-07-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Michael H. Perrott

    IPC: H03L7/099 ,  H03M3/00 ,  G04F10/00 ,  H03L7/08

    CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

    Abstract: A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

    Abstract translation: 锁相环（PLL）包括时间到电压转换器，以将参考信号和PLL的反馈信号之间的相位误差转换成一个或多个电压信号。 基于振荡器的模数转换器（ADC）接收一个或多个电压信号，并根据电压控制一个或多个振荡器。 基于振荡器的ADC基于一个或多个振荡器的频率来确定对应于相位误差的数字值。

    Capacitance-to-digital converter utilizing digital feedback and auxiliary DAC
    4.
    发明授权
    Capacitance-to-digital converter utilizing digital feedback and auxiliary DAC 有权
    采用数字反馈和辅助DAC的电容数字转换器

    公开(公告)号：US09385747B1

    公开(公告)日：2016-07-05

    申请号：US14575167

    申请日：2014-12-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Michael H. Perrott ,  Louis Nervegna

    IPC: H03M3/00

    CPC classification number: H03M3/362 ,  G01D5/24 ,  G01N27/26 ,  G01R17/105 ,  G01R27/2605 ,  H03M3/464 ,  H03M3/476 ,  H03M3/496 ,  Y10T307/729

    Abstract: A capacitance-to-digital converter circuit utilizes a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.

    Abstract translation: 电容数字转换器电路利用电容器桥电路来感测桥式电路中感测电容器和固定电容器之间的电容差。 感测电容器根据感测参数而变化。 辅助电容器数模转换器（DAC）耦合到电容器桥接电路以消除感测到的差异。 模数转换器（ADC）接收由电容器桥电路和辅助电容DAC产生的信号，并将接收的信号转换为数字信号。 数字累加器累加ADC输出，其输出表示感测电容器和固定电容器之间的电容差。 累加器输出用于控制辅助电容DAC以抵消感测电容器和固定电容器之间的电容差。 累加器输出也为电容 - 数字电路输出提供了基础。

    Fractional-N Phase-Locked Loop
    5.
    发明申请
    Fractional-N Phase-Locked Loop 有权
    分数N锁相环

    公开(公告)号：US20160112053A1

    公开(公告)日：2016-04-21

    申请号：US14985985

    申请日：2015-12-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Michael H. Perrott

    IPC: H03L7/08 ,  H03M1/66 ,  G04F10/00 ,  H03M1/08 ,  H03L7/099 ,  H03M3/00

    CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

    Abstract: A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

    Abstract translation: 锁相环（PLL）包括时间到电压转换器，以将参考信号和PLL的反馈信号之间的相位误差转换成一个或多个电压信号。 基于振荡器的模数转换器（ADC）接收一个或多个电压信号，并根据电压控制一个或多个振荡器。 基于振荡器的ADC基于一个或多个振荡器的频率来确定对应于相位误差的数字值。

    CANCELLATION OF SPURIOUS TONES WITHIN A PHASE-LOCKED LOOP WITH A TIME-TO-DIGITAL CONVERTER
    6.
    发明申请
    CANCELLATION OF SPURIOUS TONES WITHIN A PHASE-LOCKED LOOP WITH A TIME-TO-DIGITAL CONVERTER 有权
    使用时间到数字转换器取消在相位锁定环路中的SPONIOUS TONES

    公开(公告)号：US20150145567A1

    公开(公告)日：2015-05-28

    申请号：US14448458

    申请日：2014-07-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Michael H. Perrott

    IPC: H03L7/093

    CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

    Abstract: A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

    Abstract translation: 锁相环（PLL）包括杂散消除电路，其接收指示第一频率的残留信号并且接收残留相位误差信号并产生杂散消除信号。 求和电路将杂散消除信号和对应于PLL中的参考信号和反馈信号之间的相位差的第一相位误差信号相结合，并产生在第一频率具有降低的杂散音调的第二相位误差信号。

    TIME-TO-VOLTAGE CONVERTER USING A CAPACITOR BASED DIGITAL TO ANALOG CONVERTER FOR QUANTIZATION NOISE CANCELLATION
    9.
    发明申请
    TIME-TO-VOLTAGE CONVERTER USING A CAPACITOR BASED DIGITAL TO ANALOG CONVERTER FOR QUANTIZATION NOISE CANCELLATION 有权
    使用基于电容器的数字转换器进行定时噪声消除的模拟转换器的时间到电压转换器

    公开(公告)号：US20150145569A1

    公开(公告)日：2015-05-28

    申请号：US14448466

    申请日：2014-07-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Michael H. Perrott

    IPC: H03M1/08 ,  H02M3/07 ,  H03M1/66 ,  H03L7/08

    CPC classification number: H03L7/0802 ,  G04F10/005 ,  H02M3/07 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/66 ,  H03M3/358 ,  H03M3/368 ,  H03M7/3004

    Abstract: Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.

    Abstract translation: 使用基于电容的数/模转换器（DAC）来消除分数N锁相环（PLL）中的量化噪声。 在PLL中的参考信号和反馈信号之间检测到相位误差。 电荷泵电路基于相位误差对第一电容器电路充电，以产生与相位误差相对应的相位误差电压。 基于电容器的DAC基于与量化误差对应的数字值产生量化误差校正电压，然后将其与相位误差电压组合以消除量化误差。

    Hybrid analog and digital control of oscillator frequency
    10.
    发明授权
    Hybrid analog and digital control of oscillator frequency 有权

    公开(公告)号：US09705514B2

    公开(公告)日：2017-07-11

    申请号：US14554798

    申请日：2014-11-26

    Applicant: Silicon Laboratories Inc.

    Inventor： Michael H. Perrott

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/093

    CPC classification number: H03L7/0991 ,  H03L7/0802 ,  H03L7/093 ,  H03L7/0994

    Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.

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