公开(公告)号：US20140138791A1

公开(公告)日：2014-05-22

申请号：US13753930

申请日：2013-01-30

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi Che Lai

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US08952528B2

公开(公告)日：2015-02-10

申请号：US13753930

申请日：2013-01-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi Che Lai

IPC: H01L33/02 ,  H01L49/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US20140077387A1

公开(公告)日：2014-03-20

申请号：US13682103

申请日：2012-11-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Chian Liao ,  Yi Che Lai

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract translation: 提供一种半导体封装的制造方法，其包括以下步骤：将衬底切割成多个中介层; 将所述插入件布置在载体上，其中所述插入件彼此间隔一定距离; 在每个所述插入件上设置至少一个半导体元件; 形成密封剂以封装所述插入件和所述半导体元件; 并移除载体。 因此，通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止成品封装因内插件不良而被浪费。