公开(公告)号：US12255141B2

公开(公告)日：2025-03-18

申请号：US18410874

申请日：2024-01-11

Applicant: SOCIONEXT INC.

Inventor： Hideyuki Komuro ,  Junji Iwahori

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US12274091B2

公开(公告)日：2025-04-08

申请号：US18461371

申请日：2023-09-05

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H10D84/90 ,  H10D30/60 ,  H10D84/01 ,  H10D84/03 ,  H10D84/80 ,  H10D89/10

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US11916056B2

公开(公告)日：2024-02-27

申请号：US17069235

申请日：2020-10-13

Applicant: SOCIONEXT INC.

Inventor： Junji Iwahori

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/118 ,  H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L29/78 ,  G11C13/00

CPC classification number: H01L27/0207 ,  G11C13/003 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/0886 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/785 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: A semiconductor integrated circuit device includes a standard cell having a plurality of height regions. A plurality of partial circuits having an identical function and each operating in response to common signals S and NS are arranged in any one of the height regions. A metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits, and a metal interconnect forming part of a supply path for the common signal S is arranged in the height region so as to be connected to the partial circuits.

公开(公告)号：US11342412B2

公开(公告)日：2022-05-24

申请号：US16897809

申请日：2020-06-10

Applicant: SOCIONEXT INC.

Inventor： Junji Iwahori

IPC: H01L29/06 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78

Abstract: A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

公开(公告)号：US12142606B2

公开(公告)日：2024-11-12

申请号：US17706117

申请日：2022-03-28

Applicant: Socionext Inc.

Inventor： Junji Iwahori

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

Abstract: A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.

公开(公告)号：US11908799B2

公开(公告)日：2024-02-20

申请号：US17322570

申请日：2021-05-17

Applicant: SOCIONEXT INC.

Inventor： Hideyuki Komuro ,  Junji Iwahori

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L27/092

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US11799471B2

公开(公告)日：2023-10-24

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687 ,  H03K19/00

CPC classification number: H03K17/161 ,  H03K17/6871 ,  H03K19/0008

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US11784188B2

公开(公告)日：2023-10-10

申请号：US17838895

申请日：2022-06-13

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/78 ,  H01L2027/11812 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11892

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US10700095B2

公开(公告)日：2020-06-30

申请号：US16228319

申请日：2018-12-20

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US12205953B2

公开(公告)日：2025-01-21

申请号：US18540220

申请日：2023-12-14

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L21/82 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.