公开(公告)号：US5644526A

公开(公告)日：1997-07-01

申请号：US538302

申请日：1995-10-02

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L23/528 ,  H01L27/115 ,  G11C5/02 ,  G11C5/06 ,  G11C11/34 ,  G11C11/50

CPC classification number: H01L27/115 ,  H01L23/528 ,  H01L2924/0002

Abstract: The integrated circuit tolerant of large manufacturing defects comprising a first plurality of first conductors made of a first material with relatively low conductivity and each having a plurality of first electrical connection points arranged along itself and a second corresponding plurality of second conductors made of a second material with relatively high conductivity and each having a plurality of second electrical connection points arranged along itself and said plurality of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and the second conductors are interrupted between some second consecutive points in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors.

Abstract translation: 所述集成电路容许大的制造缺陷包括由具有相对低导电性的第一材料制成的第一多个第一导体，并且每个具有沿其自身布置的多个第一电连接点和由第二材料制成的第二对应的多个第二导体 具有相对较高的导电性，并且每个具有沿其自身布置的多个第二电连接点，并且所述多个第一点分别以这样的方式电连接到所述多个第二点，以便降低第一导体的串联电阻，并且第二导体 导体在一些第二连续点之间被中断，以使集成电路的相对较大的区域不被第二导体穿过。

公开(公告)号：US5081056A

公开(公告)日：1992-01-14

申请号：US506309

申请日：1990-04-06

Applicant: Stefano Mazzali ,  Massimo Melanotte ,  Luisa Masini ,  Mario Sali

Inventor： Stefano Mazzali ,  Massimo Melanotte ,  Luisa Masini ,  Mario Sali

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11519 ,  H01L27/115 ,  H01L27/11517

Abstract: A process for fabricating an integrated memory matrix of EPROM cells having a "tablecloth" organization, with source and drain lines parallel among each other and running between parallel strips of isolating field oxide, floating gate structures formed between said source and drain lines and control gate lines running parallel among each other and perpendicularly to said source and drain lines and over said floating gate structures, utilizes a mask through which a stack, formed by a second level polysilicon layer, an interpoly isolating dielectric layer, a first level polysilicon layer and a gate oxide layer, is etched for defining in a longitudinal sense the gate structures (i.e. the channel length) of the EPROM cells. The gate structures are subsequently defined in a transversal sense by etching through another mask a stack comprising a third level polysilicon layer deposited directly over said second level polysilicon layer, said interpoly dielectric layer and said first level polysilicon layer. Said other mask also defines control gate lines running perpendicularly to said parallel drain, source and field oxide lines.

公开(公告)号：US5028979A

公开(公告)日：1991-07-02

申请号：US488148

申请日：1990-03-05

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L29/7885

Abstract: The table cloth matrix comprises a semiconductor substrate, wherein there are contained in deep layers, under strips of field oxide, source lines and drain lines parallel to one another, areas of floating gate connecting said source lines and drain lines and control gate lines, parallel to one another and perpendicular to said source lines and drain lines, in a condition superimposed over said floating gate areas. Each source line is alternated with two drain lines separated by an insulation zone, so that each drain line is associated with a single row of matrix cells.

公开(公告)号：US06762452B2

公开(公告)日：2004-07-13

申请号：US10325289

申请日：2002-12-20

Applicant: Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

Inventor： Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

IPC: H01L29788

CPC classification number: H01L27/11521

Abstract: A memory device may include a semiconductor substrate, an oxide layer defining spaced apart active areas in the semiconductor substrate, and a floating gate region on each respective active area. The floating gate region may have sidewalls that are slanted with respect to a surface of the semiconductor substrate. Moreover, the memory device may also include a plug in the oxide layer.

Abstract translation: 存储器件可以包括半导体衬底，在半导体衬底中限定间隔开的有源区的氧化物层，以及每个相应的有源区上的浮动栅区。 浮栅区域可以具有相对于半导体衬底的表面倾斜的侧壁。 此外，存储器件还可以包括氧化物层中的插塞。

公开(公告)号：US5122473A

公开(公告)日：1992-06-16

申请号：US596301

申请日：1990-10-12

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L27/08

CPC classification number: H01L21/28123 ,  H01L21/76224

Abstract: Through a process perfectly suitable for fabricating integrated MISFET devices with an extremely high packing density, the field isolation structure and the gate structures of MISFET devices are simultaneously formed while attending an excellent planarity of the front of the wafer without the need of particularly burdensome techniques in order to preserve the crystallographic integrity of the substrate which is often negatively affected through conventional nitride process or by the etching of the silicon substrate as in BOX isolation processes. A patterned matrix layer of polycrystalline silicon is used for masking the active areas from the isolation implantation and from a subsequent low pressure chemical vapor deposition of a TEOS layer having a thickness substantially equal to the thickness of the masking matrix layer of polycrystalline silicon to form the field isolation structure. After having planarized the surface and exposed completely the top surfaces of the masking portions of the polycrystalline silicon matrix layer, a second layer of polycrystalline silicon is deposited and thereafter the polycrystalline silicon is doped. Finally the doped polycrystalline silicon is patterned by masking and etching steps for defining the gate structures.

公开(公告)号：US5036018A

公开(公告)日：1991-07-30

申请号：US224102

申请日：1988-07-25

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A method of manufacturing memory cells is described, wherein the great selectivity of polysilicon etching with respect to oxide is employed for the elimination of the self-aligned polysilicon mask for the definition of the floating gate of the EPROM cell. In fact, according to the invention, the mask for the formation of the source and drain regions of one of the CMOS transistors is used for the removal of the oxide separating the two layers of polysilicon on the active region defining a memory cell, and the mask for the formation of the source and drain regions of the other CMOS transistor is employed for the removal of the lower layer of polysilicon around the floating gate of the memory cell, wherein the silicon portions which are not to be removed are covered by oxide.

公开(公告)号：US06498083B2

公开(公告)日：2002-12-24

申请号：US09750449

申请日：2000-12-28

Applicant: Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

Inventor： Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

IPC: H01L214763

CPC classification number: H01L27/11521

Abstract: A method is provided for manufacturing electronic non-volatile memory devices on a semiconductor substrate including a matrix of memory cells having floating gate regions formed on respective active areas and an oxide layer separating the active areas. The method may include forming sidewalls of the floating gate regions that are slanted with respect to a surface of the semiconductor substrate, forming a trench in the oxide layer following the formation of the floating gate regions, and forming a plug of polycrystalline silicon in the trench. The slanted sidewalls of the floating gate regions provide a leading for the formation of upper layers.

Abstract translation: 提供了一种用于在半导体衬底上制造电子非易失性存储器件的方法，该半导体衬底包括具有形成在各自的有源区上的浮动栅极区域和分离有源区域的氧化物层的存储器单元的矩阵。 该方法可以包括形成相对于半导体衬底的表面倾斜的浮动栅极区域的侧壁，在形成浮动栅极区域之后在氧化物层中形成沟槽，以及在沟槽中形成多晶硅插塞 。 浮动栅极区域的倾斜侧壁提供用于形成上层的引导。

公开(公告)号：US5590075A

公开(公告)日：1996-12-31

申请号：US479081

申请日：1995-06-07

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/10 ,  G11C29/24 ,  G11C29/52 ,  G11C29/56 ,  G11C7/00

CPC classification number: G11C29/82 ,  G11C29/10 ,  G11C29/24 ,  G11C29/52

Abstract: A method for testing an electrically erasable and programmable memory device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, comprises the steps of: programing all the memory cells of the memory device; submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; reading the information stored in all the memory cells of the memory device; memorizing the addresses of defective memory cells which have been read as erased memory cell; storing the addresses of the defective memory cells in redundancy registers associated to redundancy memory cells which must substitute the defective memory cells.

Abstract translation: 一种用于测试电可擦除和可编程的存储器件的方法，包括存储器单元矩阵和功能代替有缺陷存储器单元的冗余存储单元，包括以下步骤：对存储器件的所有存储单元进行编程; 将存储器件的所有存储单元提交到比存储器单元的平均擦除时间短得多的时间的初步电擦除; 读取存储在存储设备的所有存储单元中的信息; 存储被读取为已擦除存储单元的有缺陷的存储单元的地址; 将有缺陷的存储器单元的地址存储在冗余存储器单元中，该冗余寄存器与必须替代有缺陷的存储器单元的冗余存储器单元相关联。

公开(公告)号：US5196914A

公开(公告)日：1993-03-23

申请号：US753028

申请日：1991-08-29

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L29/42376 ,  H01L29/7885

Abstract: A table cloth matrix of EPROM memory cells comprises a semiconductor substrate, parallel source lines and drain lines, floating gate areas interposed in a checkerboard pattern between the source lines and the drain lines and control gate lines, parallel to one another and perpendicular to the source lines and to the drain lines. There are obtained in the semiconductor substrate extensive oxide areas, with which the floating gates are in contact by means of their asymmetrical lateral fin.

Abstract translation: EPROM存储单元的桌布矩阵包括半导体衬底，平行的源极线和漏极线，在源极线和漏极线之间的棋盘图案中插入的浮动栅极区域和控制栅极线彼此平行并垂直于源极 线路和排水管线。 在半导体衬底中获得了大量的氧化物区域，浮动栅极通过它们的非对称横向翅片与之接触。

公开(公告)号：US5005060A

公开(公告)日：1991-04-02

申请号：US326809

申请日：1989-03-21

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L29/7885

Abstract: The memory matrix comprises parallel and alternating source and drain lines, floating gate areas placed between the source and drain lines and control gate lines parallel to each other and perpendicular to the source and drain lines superimposed on the floating gate areas. The floating gate areas are arranged in rows parallel to the source and drain lines in positions longitudinally staggered in relation to those of the adjacent row in such a manner that the floating gate areas of one row underlie a first plurality of control gate lines and the floating gate areas of the adjacent row underlie a second plurality alternating with the first of the control gate lines. The floating gate areas together with the adjacent source and drain lines and with the superimposed control gate lines define respective EPROM cells arranged in a staggered manner in the memory matrix.