公开(公告)号：US5889701A

公开(公告)日：1999-03-30

申请号：US99160

申请日：1998-06-18

申请人： Sunae Kang ,  Rafael G. San Luis, Jr. ,  Derek R. Curd ,  Ronald J. Mack

发明人： Sunae Kang ,  Rafael G. San Luis, Jr. ,  Derek R. Curd ,  Ronald J. Mack

IPC分类号： G06F11/00 ,  G11C16/30 ,  G11C29/44 ,  G11C29/50 ,  G11C16/04

CPC分类号： G06F11/006 ,  G11C16/30 ,  G11C29/44 ,  G11C29/50

摘要： A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.

摘要翻译： 一个新颖的测试程序用于确定CPLD中闪存阵列的最佳可编程电荷泵电平。 根据本发明的方法，自动化测试仪通过电荷泵代码的所有组合进行步骤，并尝试以每个电压组合组合闪速存储器。 对于每个组合，测试结果（通过或失败）被记录并存储到地图或数组中。 通过泵代码窗口的中心作为起始参考点。 下一步是验证与起始参考点对应的泵代码组合相关的实际电压电平。 将参考泵代码装载到器件中，并测量相应的闪存单元电压电平。 如果测量的电压电平不在优选范围内，则测试仪将通过调节泵代码自动调整到优选范围。

公开(公告)号：US5689516A

公开(公告)日：1997-11-18

申请号：US670916

申请日：1996-06-26

申请人： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

发明人： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F11/00

CPC分类号： G01R31/318516 ,  G01R31/318558 ,  G06F11/2215

摘要： A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

摘要翻译： 可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

公开(公告)号：US5898618A

公开(公告)日：1999-04-27

申请号：US12677

申请日：1998-01-23

申请人： Shankar Lakkapragada ,  Derek R. Curd

发明人： Shankar Lakkapragada ,  Derek R. Curd

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C16/06

CPC分类号： G11C16/30

摘要： A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage. The first and second resistors form a resistive divider that allows the predetermined reference voltage to track changes in the on-chip voltage source.

摘要翻译： 可编程逻辑器件（PLD）对PLD的存储器元件执行自检空白校验擦除验证操作，以验证它们在编程之前被擦除。 提供增强的参考电压源以可靠地产生预定电压电平的参考源电压，而不管片上电源电压和温度变化的变化。 参考电压源包括连接在片上电压源和输出节点之间的第一电阻器，连接到输出节点的第二电阻器和连接在第二电阻器和地之间的参考电压调节电路。 参考电压调节电路是可编程的，以响应于输入信号，通过一个或多个电阻元件选择性地将输出节点连接到地，使得输出节点保持在预定参考电压。 第一和第二电阻器形成电阻分压器，其允许预定参考电压跟踪片上电压源的变化。

公开(公告)号：US5734868A

公开(公告)日：1998-03-31

申请号：US512796

申请日：1995-08-09

申请人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

发明人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

IPC分类号： H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  H03K19/77

CPC分类号： H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

摘要： An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

摘要翻译： 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

公开(公告)号：US06907595B2

公开(公告)日：2005-06-14

申请号：US10319051

申请日：2002-12-13

申请人： Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck ,  Stephen W. Trynosky ,  Jeffrey V. Lindholm ,  Trevor J. Bauer

发明人： Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck ,  Stephen W. Trynosky ,  Jeffrey V. Lindholm ,  Trevor J. Bauer

IPC分类号： G06F15/78 ,  G06F17/50

CPC分类号： G06F15/7867

摘要： A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

摘要翻译： 使用由处理器控制的读 - 修改 - 写入方案来部分地重新配置可编程逻辑器件，例如现场可编程门阵列。 部分重新配置包括（1）将一组配置数据值加载到可编程逻辑器件的配置存储器阵列中，从而配置可编程逻辑器件; （2）从配置存储器阵列读取配置数据值的第一帧; （3）修改配置数据值的第一帧中的配置数据值的子集，由此创建配置数据值的第一修改帧; 和（4）用配置数据值的第一修改帧重写配置存储器阵列中的配置数据值的第一帧，从而部分地重新配置可编程逻辑器件。 读取，修改和重写的步骤在处理器的控制下执行。

公开(公告)号：US06278327B1

公开(公告)日：2001-08-21

申请号：US09374473

申请日：1999-08-13

申请人： Derek R. Curd ,  Fariba Farahanchi

发明人： Derek R. Curd ,  Fariba Farahanchi

IPC分类号： H03F316

CPC分类号： G11C16/30 ,  G11C5/143

摘要： A negative voltage detector is disclosed wherein a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider of the present invention allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

摘要翻译： 公开了一种负电压检测器，其中使用电阻分压器电路将负电压转换成标准CMOS逻辑低或逻辑高值。 由本发明的负分压器消耗的小面积允许多个器件放置在逻辑器件内，而不会消耗逻辑器件上的大量面积。 此外，放置的多个器件可以通过简单调整器件组件来检测不同的负电压阈值。

公开(公告)号：US06172518B2

公开(公告)日：2001-01-09

申请号：US09360111

申请日：1999-07-23

申请人： Jesse H. Jenkins, IV. ,  Jeffrey H. Seltzer ,  Derek R. Curd

发明人： Jesse H. Jenkins, IV. ,  Jeffrey H. Seltzer ,  Derek R. Curd

IPC分类号： G06F738

CPC分类号： H03K19/17784

摘要： A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed. No specific input/output pins are required; in fact, no external connections are required at all, though one or more may be used as inputs to the control function block logic. In some embodiments, power management can be accomplished using internal, on-chip signals alone. The pin-locking capabilities (compatibility) of conventional PLD designs are not affected and all function blocks remain identical, preserving maximum design flexibility for users.

摘要翻译： 一种使用可编程连接和废料逻辑来最小化可编程逻辑器件（PLD）中功率使用的方法，以创建通用的电源管理方案。 可以关闭PLD中的单个产品术语，从而节省电力，而不会导致现有技术中看到的上电和稳定时间延迟。 电源管理不限于任何一个功能块，除非经过编程，否则整个设备也不能关闭电源。 存在于PLD中的所有常规逻辑功能对于电源管理元件是可用的，在一个实施例中允许将标准功能块编程为操作作为控制功能块。 该逻辑功能包括但不限于内部反馈，组合功能和寄存器功能。 由于使用了从用户编程和小型可编程连接遗留下来的废料逻辑资源，所以需要最小的附加芯片表面积。 不需要特定的输入/输出引脚; 事实上，根本不需要外部连接，尽管一个或多个可以用作控制功能块逻辑的输入。 在一些实施例中，可以仅使用内部片上信号来实现功率管理。 传统PLD设计的引脚锁定功能（兼容性）不受影响，所有功能块保持不变，为用户保留最大的设计灵活性。

公开(公告)号：US6121795A

公开(公告)日：2000-09-19

申请号：US31389

申请日：1998-02-26

申请人： Derek R. Curd ,  Hy V. Nguyen

发明人： Derek R. Curd ,  Hy V. Nguyen

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018592 ,  H03K19/00315

摘要： An input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal of an integrated circuit device, such as a Programmable Logic Device (PLD). The I/O circuit includes pull-up and pull-down transistors for generating output signals on the I/O terminal in an output mode, and an isolation transistor for limiting the voltage level transmitted to the pull-up transistor from the I/O terminal in an input mode. The isolation transistor is formed with a thicker gate oxide and a longer channel length than that of the pull-up and pull-down transistors, thereby allowing the isolation transistor to withstand voltages greater than Vcc of the PLD without damage. The isolation transistor is controlled using a charge pump provided on the PLD for programming non-volatile memory cells (e.g., EPROM, EEPROM or flash EPROM cells). The isolation transistor is produced during the same process steps used to produce high voltage transistors associated with the non-volatile memory cells.

摘要翻译： 用于在诸如可编程逻辑器件（PLD）的集成电路器件的I / O端子上传输输入信号或从其接收输入信号的输入/输出（I / O）电路。 I / O电路包括用于在输出模式下在I / O端子上产生输出信号的上拉和下拉晶体管，以及用于限制从I / O传输到上拉晶体管的电压电平的隔离晶体管 终端处于输入模式。 隔离晶体管形成有比上拉和下拉晶体管更厚的栅极氧化物和更长的沟道长度，从而允许隔离晶体管承受大于PLD的Vcc的电压而不损坏。 使用在PLD上提供的用于编程非易失性存储器单元（例如，EPROM，EEPROM或闪存EPROM单元）的电荷泵来控制隔离晶体管。 在用于产生与非易失性存储器单元相关联的高电压晶体管的相同工艺步骤期间产生隔离晶体管。

公开(公告)号：US06920627B2

公开(公告)日：2005-07-19

申请号：US10377857

申请日：2003-02-28

申请人： Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Prasanna Sundararajan ,  Eric R. Keller ,  Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck

发明人： Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Prasanna Sundararajan ,  Eric R. Keller ,  Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck

IPC分类号： G06F15/78 ,  H03K19/00 ,  H03K19/177 ,  G06F17/50

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17756

摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

公开(公告)号：US06549016B1

公开(公告)日：2003-04-15

申请号：US09896158

申请日：2001-06-28

申请人： Derek R. Curd ,  Fariba Farahanchi

发明人： Derek R. Curd ,  Fariba Farahanchi

IPC分类号： G01R3108

CPC分类号： G11C16/30 ,  G11C5/143

摘要： A negative voltage detector including a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

摘要翻译： 使用包括电阻分压器电路的负电压检测器将负电压转换为标准CMOS逻辑低电平或逻辑高电平值。 负分压器消耗的小面积允许多个器件放置在逻辑器件中，而不会消耗逻辑器件上的大量面积。 此外，放置的多个器件可以通过简单调整器件组件来检测不同的负电压阈值。