公开(公告)号：US11977407B2

公开(公告)日：2024-05-07

申请号：US17683185

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Apoorva Bhatia ,  Pranav Kumar ,  Abhrarup Barman Roy ,  Peeyoosh Mirajkar ,  Raghavendra Reddy

IPC: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

CPC classification number: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.

公开(公告)号：US11387834B1

公开(公告)日：2022-07-12

申请号：US17319819

申请日：2021-05-13

Applicant: Texas Instruments Incorporated

Inventor： Pranav Kumar ,  Abhrarup Barman Roy ,  Apoorva Bhatia ,  Arpan Sureshbhai Thakkar ,  Jagdish Chand

IPC: H03L7/091 ,  H03L7/18 ,  H03L7/081 ,  H03L7/099 ,  H03L7/089

Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.

公开(公告)号：US11290118B2

公开(公告)日：2022-03-29

申请号：US17128791

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Theertham ,  Jagdish Chand ,  Yogesh Darwhekar ,  Subhashish Mukherjee ,  Jayawardan Janardhanan ,  Uday Kiran Meda ,  Arpan Sureshbhai Thakkar ,  Apoorva Bhatia ,  Pranav Kumar

IPC: H03L7/23 ,  H03M1/66 ,  H03L7/085 ,  H03L7/099

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

公开(公告)号：US10236826B1

公开(公告)日：2019-03-19

申请号：US16000972

申请日：2018-06-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Darwhekar ,  Apoorva Bhatia ,  Subhashish Mukherjee

IPC: H04B1/26 ,  H03B5/18 ,  H04B1/16 ,  H04B1/04 ,  H03D7/14

Abstract: A down converter, including first and second biasing circuits, mixer, and transformer coupled to receive amplifier output signal. The first and second biasing circuits each include a biasing transistor and a first and second node, respectively. Mixer includes first and second transistors coupled to first node and third and fourth transistors coupled to second node. The second and fourth transistors are coupled to a third node. The first and third transistors are coupled to a fourth node. Mixer also includes a first resistor coupled to the fourth node and a supply voltage node and a second resistor coupled to the third node and a supply voltage node. Transformer includes a primary winding coupled to receive the amplifier output signal and to a supply voltage and a secondary winding coupled to mixer and first biasing circuit at first node and coupled to mixer and second biasing circuit at second node.