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    MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME
    1.
    发明公开
    MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME 审中-公开

    公开(公告)号：US20230195658A1

    公开(公告)日：2023-06-22

    申请号：US17558278

    申请日：2021-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad WU ,  Abhishek SHANKAR ,  Mihir Narendra MODY ,  Gregory Raymond SHURTZ ,  Jason A. T. JONES ,  Hemant Vijay Kumar HARIYANI

    IPC: G06F13/16

    CPC classification number: G06F13/1647

    Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

    MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME
    2.
    发明公开
    MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME 审中-公开

    公开(公告)号：US20240211414A1

    公开(公告)日：2024-06-27

    申请号：US18599649

    申请日：2024-03-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad WU ,  Abhishek SHANKAR ,  Mihir Narendra MODY ,  Gregory Raymond SHURTZ ,  Jason A.T. JONES ,  Hemant Vijay Kumar HARIYANI

    IPC: G06F13/16

    CPC classification number: G06F13/1647

    Abstract: Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues. Each of the external memory arbitration modules also applies an arbitration algorithm to arbitrate among memory requests presented by the requestor arbitration modules.

    NON-STALLING, NON-BLOCKING TRANSLATION LOOKASIDE BUFFER INVALIDATION
    3.
    发明申请
    NON-STALLING, NON-BLOCKING TRANSLATION LOOKASIDE BUFFER INVALIDATION 有权

    公开(公告)号：US20210109867A1

    公开(公告)日：2021-04-15

    申请号：US17068721

    申请日：2020-10-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad WU

    IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/0891 ,  G06F9/46 ,  H03M13/15

    Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

    TRANSLATION LOOKASIDE BUFFER PREWARMING
    5.
    发明申请
    TRANSLATION LOOKASIDE BUFFER PREWARMING 有权

    公开(公告)号：US20210109866A1

    公开(公告)日：2021-04-15

    申请号：US17068713

    申请日：2020-10-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad WU

    IPC: G06F12/1027 ,  G06F12/0862 ,  G06F12/1009 ,  G06F9/48

    Abstract: A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.

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