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公开(公告)号：US20240259010A1
公开(公告)日：2024-08-01
申请号：US18455656
申请日：2023-08-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Xiaochun Zhao , Abidur Rahman , Eung Jung Kim , Tianhong Yang , Huijuan Li
IPC: H03K17/0812
CPC classification number: H03K17/0812
Abstract: A transistor is coupled between a first voltage input and a voltage output in a first current path. First circuitry is coupled to a second voltage input, a control terminal of the transistor, and the voltage output. Second circuitry is coupled between the control terminal and ground in a second current path and between the control terminal and ground in a third current path parallel to the second current path. The second current path includes the control terminal, first and second terminals of the second circuitry, and ground. The third current path includes the control terminal, a second and the third terminal of the second circuitry, and ground. Third circuitry is coupled between the control terminal and the voltage output in a fourth current path. The fourth current path includes the control terminal, first and second terminals of the third circuitry, and the voltage output.
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公开(公告)号：US12237662B2
公开(公告)日：2025-02-25
申请号：US18469109
申请日：2023-09-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eung Jung Kim , Wenchao Qu
Abstract: In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.
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公开(公告)号：US20250048721A1
公开(公告)日：2025-02-06
申请号：US18228385
申请日：2023-07-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eung Jung Kim , Thomas Grebs , Sunglyong Kim , Sungho Beck , Wei Fu , Xiaochun Zhao , Arjun Pankaj
IPC: H01L29/78 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/786
Abstract: Described examples include an integrated circuit having first and second transistors. The first transistor includes a plurality of trenches extending into a semiconductor substrate and a plurality of source regions, each source region located between a pair of adjacent trenches. A first source terminal is connected to the plurality of source regions. The second transistor includes a central source region between a pair of the trenches and a second source terminal connected to the central source region. The second source terminal is conductively isolated from the first source terminal.
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公开(公告)号：US11184000B2
公开(公告)日：2021-11-23
申请号：US16001551
申请日：2018-06-06
Applicant: Texas Instruments Incorporated
Inventor： Eung Jung Kim , Sualp Aras , Abidur Rahman
IPC: H03K17/082 , H03K17/14 , G01R1/067 , H03K17/0814 , H03K17/16 , H03K17/0812 , G01R31/26
Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.
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公开(公告)号：US20190214980A1
公开(公告)日：2019-07-11
申请号：US16001551
申请日：2018-06-06
Applicant: Texas Instruments Incorporated
Inventor： Eung Jung Kim , Sualp Aras , Abidur Rahman
IPC: H03K17/082 , H03K17/14 , G01R1/067 , G01R31/26 , H03K17/16 , H03K17/0812 , H03K17/0814
Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.
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Patent Agency Ranking
公开(公告)号：US20250112629A1
公开(公告)日：2025-04-03
申请号：US18374202
申请日：2023-09-28
Applicant: Texas Instruments Incorporated
Inventor： Eung Jung Kim , Xiaochun Zhao , Abidur Rahman , Sualp Aras
IPC: H03K17/0812
Abstract: An example apparatus includes: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; first driver circuitry having a terminal coupled to the control terminal of the first transistor; second driver circuitry having a terminal coupled to the control terminal of the second transistor; and gate balancing circuitry having a first terminal and a second terminal, the first terminal of the gate balancing circuitry coupled to the control terminal of the first transistor and the terminal of the first driver circuitry, the second terminal of the gate balancing circuitry coupled to the control terminal of the second transistor.
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公开(公告)号：US11574902B2
公开(公告)日：2023-02-07
申请号：US16264065
申请日：2019-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eung Jung Kim , Kyle Clifton Schulmeyer , Sualp Aras , Md Abidur Rahman , Xiaochun Zhao
Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.
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公开(公告)号：US20220214226A1
公开(公告)日：2022-07-07
申请号：US17706113
申请日：2022-03-28
Applicant: Texas Instruments Incorporated
Inventor： Eung Jung Kim , Abidur Rahman
Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
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公开(公告)号：US10554203B1
公开(公告)日：2020-02-04
申请号：US16206317
申请日：2018-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sualp Aras , Eung Jung Kim , Abidur Md Rahman
IPC: H03K17/16 , G01R31/00 , G01R19/165
Abstract: In some examples, the disclosure includes a circuit including a power field effect transistor (FET), a gate pull-down circuit, a pull-down bias circuit, and a radio frequency (RF) detector coupled to the source terminal of the power FET and the pull-down bias circuit. In an example, the RF detector circuit is configured to detect a presence of an alternating current signal at a source terminal of the power FET when the power FET is in a non-conductive state and control the pull-down bias circuit to bias the gate pull-down circuit to create a low impedance path between a gate terminal of the power FET and the source terminal of the power FET when the power FET is in the non-conductive state and the alternating current signal is present at the source terminal of the power FET.
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公开(公告)号：US20200033198A1
公开(公告)日：2020-01-30
申请号：US16395860
申请日：2019-04-26
Applicant: Texas Instruments Incorporated
Inventor： Eung Jung Kim , Abidur Rahman
Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
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