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    IC PACKAGE WITH IMMERSION TIN ON FLANK
    2.
    发明申请
    IC PACKAGE WITH IMMERSION TIN ON FLANK 有权

    公开(公告)号：US20250046621A1

    公开(公告)日：2025-02-06

    申请号：US18362635

    申请日：2023-07-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nazila Dadvand ,  Xuan Mo Li ,  Huo Yun Duan

    IPC: H01L21/48 ,  H01L21/683 ,  H01L23/495

    Abstract: A method for forming integrated circuit (IC) packages includes mounting tape on a mold compound of a strip of flat no-leads IC packages. The method also includes sawing the mold compound of the strip of flat no-leads IC packages to form singulated IC packages mounted on the tape. The method further includes immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating on a flank of leads of the singulated IC packages.

    Copper wire bond on gold bump on semiconductor die bond pad
    3.
    发明授权
    Copper wire bond on gold bump on semiconductor die bond pad 有权

    公开(公告)号：US12283559B2

    公开(公告)日：2025-04-22

    申请号：US18071288

    申请日：2022-11-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lin Zhang ,  Huo Yun Duan ,  Xi Lin Li ,  Chen Xiong ,  Xiao Lin Kang

    IPC: H01L23/498 ,  H01L23/00

    Abstract: A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.

    DYNAMIC PLATED METAL THICKNESS FOR SEMICONDUCTOR PACKAGE
    4.
    发明申请
    DYNAMIC PLATED METAL THICKNESS FOR SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250069999A1

    公开(公告)日：2025-02-27

    申请号：US18454242

    申请日：2023-08-23

    Applicant: Texas Instruments Incorporated

    Inventor： Huo Yun Duan ,  Qin Peng ,  Tian Sheng Chen ,  Xiangrui Li ,  Hang Yan

    IPC: H01L23/495 ,  C25D3/12 ,  C25D3/30 ,  C25D3/46 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48 ,  H01L23/31

    Abstract: A semiconductor package includes a semiconductor component and a plurality of leads electrically connected to the semiconductor component. Each of the leads has a first surface, and has a second surface opposite from the first surface, with a solderable metal on the first surface and the second surface. The solderable metal has a first average thickness on the first surfaces, and has a second average thickness on the second surfaces. The second average thickness is 10 percent to 80 percent of the first average thickness. The semiconductor package is formed by concurrently electroplating the solderable metal on the first surfaces and on the second surfaces. The solderable metal is electroplated on the first surfaces with a first average current, and is electroplated on the second surfaces with a second average current. The second average current is 10 percent to 80 percent of the first average current.

    SEMICONDUCTOR DEVICE PACKAGE WITH WETTABLE FLANKS
    6.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE WITH WETTABLE FLANKS 有权

    公开(公告)号：US20250006510A1

    公开(公告)日：2025-01-02

    申请号：US18346164

    申请日：2023-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Yu Fu ,  Huo Yun Duan ,  Fu Ren Pang ,  Longting Li ,  Zheng Qing Fan

    IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H05K3/34

    Abstract: In a described example, an example no-lead semiconductor device package includes: a die pad in a central portion of a partially etched leadframe and terminals. The terminals include a device side surface formed in an upper layer of the partially etched leadframe, and a first exterior end in the upper layer; a board side surface formed in a lower layer of the partially etched leadframe extending from the upper layer; a second exterior end in the lower layer, the second exterior end inset from the first exterior end, and an inset portion extending from the first exterior end to the second exterior end. A semiconductor die is mounted to the die pad. Mold compound covers the semiconductor die, the second exterior end of the terminals and the inset portion of the terminals are exposed from the mold compound, with the mold compound extending along sides of the terminals.

    ULTRA-LOW THICKNESS SEMICONDUCTOR PACKAGE
    7.
    发明公开
    ULTRA-LOW THICKNESS SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240203838A1

    公开(公告)日：2024-06-20

    申请号：US18069220

    申请日：2022-12-20

    Applicant: Texas Instruments Incorporated

    Inventor： Huo Yun Duan ,  Fu Ren Pang ,  Zheng Qing Fan ,  Silijia Xie

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

    CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/48 ,  H01L2224/48245

    Abstract: An example integrated circuit (IC) package comprises a DAP having a diamond shape with four corners. The DAP has a first thickness. The IC package has at least one tie bar segment attached to a corner of the DAP. The at least one tie bar segment extends from the DAP to an edge of the IC package. The IC package has at least one contact portion positioned adjacent to a side of the DAP. The at least one contact portions has a second thickness that is greater than the first thickness of the DAP. A semiconductor die mounted on the DAP. A wire bond couples a bond pad on the semiconductor die and a selected one of the contact portions. A molding compound covers the semiconductor die and the bond wire and at least a portion of the DAP and the at least one contact portion.

    COPPER WIRE BOND ON GOLD BUMP ON SEMICONDUCTOR DIE BOND PAD
    8.
    发明申请
    COPPER WIRE BOND ON GOLD BUMP ON SEMICONDUCTOR DIE BOND PAD 有权

    公开(公告)号：US20230086535A1

    公开(公告)日：2023-03-23

    申请号：US18071288

    申请日：2022-11-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lin Zhang ,  Huo Yun Duan ,  Xi Lin Li ,  Chen Xiong ,  Xiao Lin Kang

    IPC: H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.

    Copper wire bond on gold bump on semiconductor die bond pad
    10.
    发明授权
    Copper wire bond on gold bump on semiconductor die bond pad 有权

    公开(公告)号：US11515275B2

    公开(公告)日：2022-11-29

    申请号：US16941701

    申请日：2020-07-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lin Zhang ,  Huo Yun Duan ,  Xi Lin Li ,  Chen Xiong ,  Xiao Lin Kang

    IPC: H01L23/498 ,  H01L23/00

    Abstract: A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.

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