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1.发明授权公开(公告)号：US11387834B1
公开(公告)日：2022-07-12
申请号：US17319819
申请日：2021-05-13
Applicant: Texas Instruments Incorporated
Inventor： Pranav Kumar , Abhrarup Barman Roy , Apoorva Bhatia , Arpan Sureshbhai Thakkar , Jagdish Chand
Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.
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公开(公告)号：US11290118B2
公开(公告)日：2022-03-29
申请号：US17128791
申请日：2020-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Theertham , Jagdish Chand , Yogesh Darwhekar , Subhashish Mukherjee , Jayawardan Janardhanan , Uday Kiran Meda , Arpan Sureshbhai Thakkar , Apoorva Bhatia , Pranav Kumar
Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.
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Patent Agency Ranking
公开(公告)号：US10720946B2
公开(公告)日：2020-07-21
申请号：US16361806
申请日：2019-03-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagdish Chand , Subhashish Mukherjee
Abstract: A radio frequency transmitter includes a digital-to-analog converter (DAC), a load circuit, and a modulator circuit. The load circuit is coupled to an output of the DAC. The modulator circuit is coupled to the DAC and the load circuit. The modulator circuit includes a driver circuit configured to provide a bias voltage to the load circuit, and an amplifier configured to receive an output of the DAC biased by an output of the load circuit.
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公开(公告)号：US10250248B2
公开(公告)日：2019-04-02
申请号：US16057979
申请日：2018-08-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srikanth Manian , Srinivas Theertham , Jagdish Chand , Dinesh Jain
Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
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公开(公告)号：US20180351541A1
公开(公告)日：2018-12-06
申请号：US16057979
申请日：2018-08-08
Applicant: Texas Instruments Incorporated
Inventor： Srikanth Manian , Srinivas Theertham , Jagdish Chand , Dinesh Jain
CPC classification number: H03K5/26 , H03K5/135 , H03K5/1502 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/18
Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
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公开(公告)号：US10075156B2
公开(公告)日：2018-09-11
申请号：US15673166
申请日：2017-08-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srikanth Manian , Srinivas Theertham , Jagdish Chand , Dinesh Jain
CPC classification number: H03K5/26 , H03K5/135 , H03K5/1502 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/18
Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.
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公开(公告)号：US10284238B1
公开(公告)日：2019-05-07
申请号：US16004503
申请日：2018-06-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagdish Chand , Subhashish Mukherjee
Abstract: A radio frequency transmitter includes a digital-to-analog converter (DAC), a load circuit, and a modulator circuit. The load circuit is coupled to an output of the DAC. The modulator circuit is coupled to the DAC and the load circuit. The modulator circuit includes a driver circuit configured to provide a bias voltage to the load circuit, and an amplifier configured to receive an output of the DAC biased by an output of the load circuit.
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