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公开(公告)号：US10651870B2
公开(公告)日：2020-05-12
申请号：US16141671
申请日：2018-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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公开(公告)号：US10084473B2
公开(公告)日：2018-09-25
申请号：US15455971
申请日：2017-03-10
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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公开(公告)号：US09054736B2
公开(公告)日：2015-06-09
申请号：US14100578
申请日：2013-12-09
Applicant: Texas Instruments Incorporated
Inventor： Arthur John Redfern , Kun Shi
CPC classification number: H03M3/422 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/322 , H03M3/468 , H04B1/40
Abstract: An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes shaping quantization noise in response to: a signal-to-noise ratio of the analog input signal; and a power of the converter.
Abstract translation: 模数转换器接收模拟输入信号。 模拟输入信号被转换为数字输出信号。 转换包括响应于模拟输入信号的信噪比而整形量化噪声; 和转换器的电源。
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Patent Agency Ranking
公开(公告)号：US20170187387A1
公开(公告)日：2017-06-29
申请号：US15455971
申请日：2017-03-10
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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公开(公告)号：US20140159931A1
公开(公告)日：2014-06-12
申请号：US14100578
申请日：2013-12-09
Applicant: Texas Instruments Incorporated
Inventor： Arthur John Redfern , Kun Shi
CPC classification number: H03M3/422 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/322 , H03M3/468 , H04B1/40
Abstract: An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes shaping quantization noise in response to: a signal-to-noise ratio of the analog input signal; and a power of the converter.
Abstract translation: 模数转换器接收模拟输入信号。 模拟输入信号被转换为数字输出信号。 转换包括响应于模拟输入信号的信噪比而整形量化噪声; 和转换器的电源。
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公开(公告)号：US20190222223A1
公开(公告)日：2019-07-18
申请号：US16141671
申请日：2018-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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7.发明申请Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters 有权流水线连续模拟数字转换器中的输入路径匹配公开(公告)号：US20160269045A1
公开(公告)日：2016-09-15
申请号：US15068231
申请日：2016-03-11
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
Abstract translation: 在流水线连续时间模数转换器（ADC）中的输入路径匹配的系统和方法，包括基于流水线连续时间三角调制器（CTDSM）的ADC，包括设置在连续时间输入路径中的输入延迟电路， 将模拟输入信号输入到连续时间ADC的第一求和电路。 至少一个数字延迟线设置在耦合到第一求和电路的较低级子ADC（多个流水线式子ADC）的输出与子数字 - 模拟转换器（DAC）之间， 并且在较低级的副ADC与数字噪声消除滤波器之间。 数字延迟线被配置为使得能够根据输入延迟匹配电路的过程变化来校准提供给子DAC和数字噪声消除滤波器的前级子ADC的输出延迟，以最小化残留输出 在第一个求和电路。
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公开(公告)号：US09614510B2
公开(公告)日：2017-04-04
申请号：US15068231
申请日：2016-03-11
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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