-
公开(公告)号：US20240038691A1
公开(公告)日：2024-02-01
申请号：US17877426
申请日：2022-07-29
Applicant: Texas Instruments Incorporated
Inventor： Vijaylaxmi Gumaste Khanolkar , Anindya Poddar , Hassan Omar Ali , Dibyajat Mishra , Venkatesh Srinivasan , Swaminathan Sankaran
IPC: H01L23/66 , H01Q1/22 , H01L21/56 , H01L23/00 , H01L23/498
CPC classification number: H01L23/66 , H01Q1/2283 , H01L21/565 , H01L21/561 , H01L24/96 , H01L24/97 , H01L23/49805 , H01L23/49816 , H01L23/49811 , H01L23/49833 , H01L23/49822 , H01L23/49838 , H01L24/16 , H01L2224/16225 , H01L2223/6677 , H01L2223/6683 , H01L2223/6688 , H01L2924/2027 , H01L2924/182
Abstract: In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.
-
公开(公告)号：US09614510B2
公开(公告)日：2017-04-04
申请号：US15068231
申请日：2016-03-11
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
-
3.发明申请公开(公告)号：US20150138004A1
公开(公告)日：2015-05-21
申请号：US14606533
申请日：2015-01-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Patrick Satarzadeh , Venkatesh Srinivasan , Charles Sestok
IPC: H03M3/00
Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
Abstract translation: 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
-
公开(公告)号：US20190222223A1
公开(公告)日：2019-07-18
申请号：US16141671
申请日：2018-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
-
公开(公告)号：US09531335B2
公开(公告)日：2016-12-27
申请号：US14818882
申请日：2015-08-05
Applicant: Texas Instruments Incorporated
Inventor： Harish Kundur Subramaniyan , Eric Klumperink , Venkatesh Srinivasan , Ali Kiaei , Bram Nauta
CPC classification number: H03F3/193 , H03F1/0261 , H03F1/301 , H03F1/308 , H03F1/3205 , H03F1/3217 , H03F3/3022 , H03F2200/294 , H03F2200/451 , H03F2203/30078 , H03F2203/30111
Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second-order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor.
Abstract translation: 在包括第一N沟道晶体管和第一P沟道晶体管的CMOS跨导电路中，三阶失真减小，第一N沟道晶体管和第一P沟道晶体管的栅极被耦合以接收输入信号。 第一N沟道晶体管和第一P沟道晶体管的漏极耦合到输出导体。 第一退化电阻器耦合在第一P沟道晶体管的源极和第一电源电压之间，而第二退化电阻耦合在第一N沟道晶体管的源极和第二电源电压之间。 第一低阻抗旁路电路耦合在第一P沟道晶体管和第一N沟道晶体管的源极之间。 低阻抗旁路电路通过第一N沟道晶体管和第一P沟道重新循环由第二P沟道晶体管和第一N沟道晶体管的漏极电流引起的二阶失真引起的二阶失真电流 晶体管。
-
Patent Agency Ranking
6.发明申请Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters 有权流水线连续模拟数字转换器中的输入路径匹配公开(公告)号：US20160269045A1
公开(公告)日：2016-09-15
申请号：US15068231
申请日：2016-03-11
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
Abstract translation: 在流水线连续时间模数转换器（ADC）中的输入路径匹配的系统和方法，包括基于流水线连续时间三角调制器（CTDSM）的ADC，包括设置在连续时间输入路径中的输入延迟电路， 将模拟输入信号输入到连续时间ADC的第一求和电路。 至少一个数字延迟线设置在耦合到第一求和电路的较低级子ADC（多个流水线式子ADC）的输出与子数字 - 模拟转换器（DAC）之间， 并且在较低级的副ADC与数字噪声消除滤波器之间。 数字延迟线被配置为使得能够根据输入延迟匹配电路的过程变化来校准提供给子DAC和数字噪声消除滤波器的前级子ADC的输出延迟，以最小化残留输出 在第一个求和电路。
-
7.发明授权公开(公告)号：US09413382B2
公开(公告)日：2016-08-09
申请号：US14606533
申请日：2015-01-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Patrick Satarzadeh , Venkatesh Srinivasan , Charles Sestok
Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
Abstract translation: 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
-
公开(公告)号：US10651870B2
公开(公告)日：2020-05-12
申请号：US16141671
申请日：2018-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
-
公开(公告)号：US10084473B2
公开(公告)日：2018-09-25
申请号：US15455971
申请日：2017-03-10
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
-
公开(公告)号：US20170187387A1
公开(公告)日：2017-06-29
申请号：US15455971
申请日：2017-03-10
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.016 seconds)
