公开(公告)号：US10516381B2

公开(公告)日：2019-12-24

申请号：US15858892

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： James Cooper Wainerdi ,  Luu Nguyen ,  Alexander Harvey Scheuermann ,  Matthew David Romig

IPC: H03H9/10 ,  H01L23/495 ,  H01L23/31 ,  B81B7/00 ,  H01L23/18 ,  B33Y80/00 ,  H01L21/02 ,  H01L41/053 ,  H01L41/23 ,  B29C64/00

Abstract: In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protective shell and exposed portion of the first surface of the semiconductor die. A cavity space is within an inner space of the protective shell and the first portion of the top surface of the semiconductor die.

公开(公告)号：US10077186B2

公开(公告)日：2018-09-18

申请号：US15603183

申请日：2017-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B7/00 ,  B81C1/00 ,  G01N33/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

公开(公告)号：US20170253476A1

公开(公告)日：2017-09-07

申请号：US15603183

申请日：2017-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B7/00 ,  G01N33/00 ,  H01L23/16 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

公开(公告)号：US09688530B2

公开(公告)日：2017-06-27

申请号：US14723122

申请日：2015-05-27

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B1/00 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

公开(公告)号：US20170015548A1

公开(公告)日：2017-01-19

申请号：US14963362

申请日：2015-12-09

Applicant: Texas Instruments Incorporated

Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

Abstract translation: 一种以面板格式制造具有开口腔（110a）的封装半导体器件（100）的方法; 将具有平垫（230）和对称放置的垂直柱（231）的金属片的面板尺寸网格放置（处理201）在粘合剂载带上。 将具有传感器系统的半导体芯片（工艺202）面朝下地附接到带上; 层压（工艺203）和减薄（工艺204）低CTE绝缘材料（234）以填充芯片和网格之间的间隙; 翻转（过程205）组装以去除胶带; 等离子体清洁组件正面，溅射和图案化（工艺206）跨组合均匀的金属层和任选的电镀（工艺209）金属层以形成重新布线迹线和扩展的接触垫用于组装; 层压（工艺212）跨板的绝缘加强件; 在加强件中打开（过程213）空腔以接近传感器系统; 并通过切割金属片来分割（处理214）包装的装置。

公开(公告)号：US11082028B2

公开(公告)日：2021-08-03

申请号：US16724681

申请日：2019-12-23

Applicant: Texas Instruments Incorporated

Inventor： James Cooper Wainerdi ,  Luu Nguyen ,  Alexander Harvey Scheuermann ,  Matthew David Romig

IPC: H03H9/10 ,  H01L23/495 ,  H01L23/31 ,  B81B7/00 ,  H01L23/18 ,  B29C64/00 ,  B33Y80/00 ,  H01L21/02 ,  H01L23/433 ,  H01L41/053 ,  H01L41/23

Abstract: In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protective shell and exposed portion of the first surface of the semiconductor die. A cavity space is within an inner space of the protective shell and the first portion of the top surface of the semiconductor die.

公开(公告)号：US09663357B2

公开(公告)日：2017-05-30

申请号：US14963362

申请日：2015-12-09

Applicant: Texas Instruments Incorporated

Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

IPC: H01L21/683 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

公开(公告)号：US20160347607A1

公开(公告)日：2016-12-01

申请号：US14723122

申请日：2015-05-27

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B7/00 ,  G01N27/02 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Abstract translation: 一种集成电路（“IC”）封装，包括具有顶表面和底表面的IC管芯，具有相对的第一和第二端部的中间部分的细长元件。 中间部分位于IC芯片顶表面附近。 IC封装还包括具有顶表面，底表面和相对的第一和第二横向侧表面的密封剂块。 密封剂块封装IC芯片和细长构件。 细长构件的第一和第二端部中的任一个或两个都被暴露。