公开(公告)号：US20250006776A1

公开(公告)日：2025-01-02

申请号：US18343179

申请日：2023-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Robert Visokay

IPC: H01C17/232 ,  H01C7/00 ,  H01L27/08

Abstract: An electronic device including a thermistor and a thin-film bias reference resistor in a voltage divider configuration integrated into a single die and a method of fabricating the same. In an example, the electronic device comprises a substrate including an n-well region, a thermistor formed in the n-well region, and a thin-film resistor operable as a bias resistor connected in series to the thermistor, the thin-film resistor formed in a region of the substrate isolated from the n-well region.

公开(公告)号：US11004929B2

公开(公告)日：2021-05-11

申请号：US16596972

申请日：2019-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dok Won Lee ,  Erika Lynn Mazotti ,  Mark Robert Visokay ,  William David French ,  Ricky Alan Jackson ,  Wai Lee

IPC: H01L49/02 ,  G01K7/22 ,  H01L23/522 ,  H01L27/07 ,  G01K7/16

Abstract: Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

公开(公告)号：US20250006408A1

公开(公告)日：2025-01-02

申请号：US18343092

申请日：2023-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Robert Visokay

IPC: H01C7/02 ,  H01C7/04 ,  H01C17/24 ,  H01L27/07 ,  H01L27/08

Abstract: An electronic device including a thermistor and a bias reference resistor in a voltage divider configuration integrated into a single die and a method of fabricating the same. In an example, the electronic device comprises a substrate including an n-well region, a thermistor formed in the n-well region, and a bias resistor connected in series to the thermistor, the bias resistor formed in a region of the substrate isolated from the n-well region.

公开(公告)号：US11710764B2

公开(公告)日：2023-07-25

申请号：US16020131

申请日：2018-06-27

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Sagnik Dey ,  Luigi Colombo ,  Haowen Bu ,  Scott Robert Summerfelt ,  Mark Robert Visokay ,  John Paul Campbell

IPC: H01L21/285 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L28/91 ,  H01L21/28518 ,  H01L21/306 ,  H01L21/32133

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

公开(公告)号：US10249621B2

公开(公告)日：2019-04-02

申请号：US15380546

申请日：2016-12-15

Applicant: Texas Instruments Incorporated

Inventor： Mark Robert Visokay ,  Tae S. Kim ,  Mahalingam Nandakumar ,  Eric D. Rullan ,  Gregory B. Shinn

IPC: H01L27/00 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/522 ,  H01L29/49

Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

公开(公告)号：US20140147940A1

公开(公告)日：2014-05-29

申请号：US14088572

申请日：2013-11-25

Applicant: Texas Instruments Incorporated

Inventor： Mark Robert Visokay ,  Scott Robert Summerfelt

IPC: H01L49/02 ,  C23C2/00

CPC classification number: H01L21/2855 ,  B22F3/10 ,  B22F5/00 ,  C22C28/00 ,  C22C32/001 ,  C22C32/0015 ,  C22C32/0031 ,  C22C32/0042 ,  C23C14/08 ,  C23C14/082 ,  C23C14/3414 ,  H01L21/32133 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.

Abstract translation: 用于导电氧化物的溅射靶，例如SrRuO 3，用于在集成电路中与铁电材料接触的导电膜的溅射沉积。 溅射靶是通过将导电氧化物的粉末混合物与铁电体材料的组分之一的氧化物的烧结剂烧结而形成的。 作为铁电材料的钛酸锆酸铅（PZT）的例子，烧结剂是氧化铅，氧化锆，氧化钛中的一种以上。 所得到的溅射靶具有更高的密度和更低的孔隙率，导致改进的溅射沉积膜不包括超过与该膜相邻沉积的铁电材料的原子种类的原子种类。

公开(公告)号：US20150221516A1

公开(公告)日：2015-08-06

申请号：US14682944

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Mark Robert Visokay ,  Scott Robert Summerfelt

IPC: H01L21/285 ,  H01L21/3213 ,  C23C14/08 ,  C22C32/00 ,  B22F3/10 ,  B22F5/00 ,  C22C28/00 ,  H01L49/02 ,  C23C14/34

CPC classification number: H01L21/2855 ,  B22F3/10 ,  B22F5/00 ,  C22C28/00 ,  C22C32/001 ,  C22C32/0015 ,  C22C32/0031 ,  C22C32/0042 ,  C23C14/08 ,  C23C14/082 ,  C23C14/3414 ,  H01L21/32133 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.

Abstract translation: 用于导电氧化物的溅射靶，例如SrRuO 3，用于在集成电路中与铁电材料接触的导电膜的溅射沉积。 溅射靶是通过将导电氧化物的粉末混合物与铁电体材料的组分之一的氧化物的烧结剂烧结而形成的。 作为铁电材料的钛酸锆酸铅（PZT）的例子，烧结剂是氧化铅，氧化锆，氧化钛中的一种以上。 所得到的溅射靶具有更高的密度和更低的孔隙率，导致改进的溅射沉积膜不包括超过与该膜相邻沉积的铁电材料的原子种类的原子种类。

公开(公告)号：US08822236B2

公开(公告)日：2014-09-02

申请号：US13949581

申请日：2013-07-24

Applicant: Texas Instruments Incorporated

Inventor： Bo-Yang Lin ,  Yen Lee ,  Haowen Bu ,  Mark Robert Visokay

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/115 ,  H01L21/02

CPC classification number: H01L21/02225 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57

Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

Abstract translation: 通过等离子体增强化学气相沉积（PECVD）沉积氮化硅的无氨方法。 将硅烷（SiH4）和氮（N2）的源气体提供给平行板等离子体反应器，其中能量电容耦合到等离子体，并且其中正在处理的晶片已经被放置在支撑电极处。 将低频RF能量（例如，360kHz）施加到支撑电极; 可选地，将高频RF能量（例如，13.56MHz）提供给并联电极。 工艺温度高于350℃，压力约为2.5托。 存在于所得氮化硅膜中的任何氢由N-H键而不是Si-H键结合，因此与膜更牢固地结合。 氮化硅可用作铁电材料的钝化剂，如果被氢气污染，则可能会电解。

公开(公告)号：US20130309783A1

公开(公告)日：2013-11-21

申请号：US13949581

申请日：2013-07-24

Applicant: Texas Instruments Incorporated

Inventor： Bo-Yang Lin ,  Yen Lee ,  Haowen Bu ,  Mark Robert Visokay

IPC: H01L21/02

CPC classification number: H01L21/02225 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57

Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

Abstract translation: 通过等离子体增强化学气相沉积（PECVD）沉积氮化硅的无氨方法。 将硅烷（SiH 4）和氮（N 2）的源气体提供给平行板等离子体反应器，其中能量电容耦合到等离子体，并且其中正在处理的晶片已经被放置在支撑电极处。 将低频RF能量（例如，360kHz）施加到支撑电极; 可选地，将高频RF能量（例如，13.56MHz）提供给并联电极。 工艺温度高于350℃，压力约为2.5托。 存在于所得氮化硅膜中的任何氢由N-H键而不是Si-H键结合，因此与膜更牢固地结合。 氮化硅可用作铁电材料的钝化剂，如果被氢气污染，则可能会电解。