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公开(公告)号：US20180183409A1
公开(公告)日：2018-06-28
申请号：US15852237
申请日：2017-12-22
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish , Visvesvaraya Pentakota
IPC: H03H11/24 , H03H7/25 , H03G1/00 , H03K17/687 , H01F38/14
CPC classification number: H03H11/245 , H01F38/14 , H03G1/0088 , H03G3/001 , H03G3/3052 , H03G2201/106 , H03H7/25 , H03K17/687 , H04B1/18
Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.
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公开(公告)号：US09602069B2
公开(公告)日：2017-03-21
申请号：US15254894
申请日：2016-09-01
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
CPC classification number: H03G1/0082 , H03F1/26 , H03F3/45085 , H03F3/45098 , H03F3/72 , H03F2200/294 , H03F2203/45026 , H03F2203/45202 , H03F2203/45466 , H03F2203/45494 , H03F2203/45496 , H03F2203/45504 , H03F2203/7233 , H03G1/0035 , H03G1/0088 , H03G3/001 , H03G3/3052 , H04B1/1036 , H04B1/18
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
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公开(公告)号：US11063562B2
公开(公告)日：2021-07-13
申请号：US16794319
申请日：2020-02-19
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
IPC: H03F1/22 , H03F3/19 , H03F1/02 , H03F3/191 , H03F3/45 , G02B27/01 , G06F3/01 , G06T19/00 , H03F1/32
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
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公开(公告)号：US20200209977A1
公开(公告)日：2020-07-02
申请号：US16794319
申请日：2020-02-19
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
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公开(公告)号：US10608602B2
公开(公告)日：2020-03-31
申请号：US16268552
申请日：2019-02-06
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
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Patent Agency Ranking
公开(公告)号：US20190173437A1
公开(公告)日：2019-06-06
申请号：US16268552
申请日：2019-02-06
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
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公开(公告)号：US10476542B1
公开(公告)日：2019-11-12
申请号：US16274621
申请日：2019-02-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Neeraj Shrivastava , Rajendrakumar Joish , Shagun Dusad , Visvesvaraya Pentakota
IPC: H04B1/04 , H04B1/18 , H03K17/94 , H03K19/173
Abstract: A digital step attenuator (DSA) includes a switch control circuit which receives the attenuated signal output by the DSA from a buffer and generates a tracked control signal for switches within the DSA. Some switch control circuits include a capacitor coupled to receive the buffered signal, a supply voltage, and a switch control logic sub-circuit for each switch. Each switch control logic sub-circuit receives a control signal, for either the gate or the bulk terminal of the switch, and generates the tracked control signal. In other embodiments, switch control circuits include a complementary MOSFET switching device coupled to receive a control signal, and a capacitor coupled to receive the buffered signal, both of which are connected to an output terminal for the tracked control signal. In those embodiments, the DSA includes a switch control circuit for each switch connected to the DSA output.
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公开(公告)号：US10419010B1
公开(公告)日：2019-09-17
申请号：US16217165
申请日：2018-12-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajendrakumar Joish , Himanshu Varshney
Abstract: Pipelined analog-to-digital converters (ADCs) include a flash ADC that reduces noise tones in power supply current drawn by the flash ADC. A pipelined analog-to-digital converter (ADC) includes a flash ADC and error correction circuitry coupled to the flash ADC. The flash ADC includes a plurality of latched comparators and a plurality of driver circuits. Each of the latched comparators includes an inverting output and a non-inverting output. Each of the driver circuits is coupled to one of the latched comparators, and includes an input terminal and an output terminal. In a first subset of the driver circuits the input terminal is coupled to the inverting output of one of the latched comparators. In a second subset of the driver circuits the input terminal is coupled to the non-inverting output of one of the latched comparators.
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公开(公告)号：US20180183475A1
公开(公告)日：2018-06-28
申请号：US15855052
申请日：2017-12-27
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a sampling capacitor coupled to the ADC. The DSA also includes a time dependent resistor coupled to a source voltage and to the sampling capacitor.
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公开(公告)号：US20160373079A1
公开(公告)日：2016-12-22
申请号：US15254894
申请日：2016-09-01
Applicant: Texas Instruments Incorporated
Inventor： Rajendrakumar Joish
CPC classification number: H03G1/0082 , H03F1/26 , H03F3/45085 , H03F3/45098 , H03F3/72 , H03F2200/294 , H03F2203/45026 , H03F2203/45202 , H03F2203/45466 , H03F2203/45494 , H03F2203/45496 , H03F2203/45504 , H03F2203/7233 , H03G1/0035 , H03G1/0088 , H03G3/001 , H03G3/3052 , H04B1/1036 , H04B1/18
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
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