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公开(公告)号：US09960777B2
公开(公告)日：2018-05-01
申请号：US15333659
申请日：2016-10-25
Applicant: Texas Instruments Incorporated
Inventor： Timothy Paul Duryea , Vaibhav Garg
CPC classification number: H03M1/0607 , H03K19/0005 , H03M1/1076 , H03M1/122 , H03M1/1245 , H03M1/44
Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.
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公开(公告)号：US20190025866A1
公开(公告)日：2019-01-24
申请号：US15832071
申请日：2017-12-05
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Vijayalakshmi Devarajan , Timothy Paul Duryea , Shanmuganand Chellamuthu
IPC: G05F3/26 , H03K17/687 , B60T8/1761 , B60T8/172
Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
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公开(公告)号：US20170047936A1
公开(公告)日：2017-02-16
申请号：US15333659
申请日：2016-10-25
Applicant: Texas Instruments Incorporated
Inventor： Timothy Paul Duryea , Vaibhav Garg
CPC classification number: H03M1/0607 , H03K19/0005 , H03M1/1076 , H03M1/122 , H03M1/1245 , H03M1/44
Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.
Abstract translation: 本公开描述了一种在模数转换器中使用的通道选择器，其具有用于将模拟输入转换为容错范围内的数字输出的采样电路。 信道选择器包括接收信道，诊断信道和阻抗补偿器。 当接收通道被选择用于与采样电路耦合时，接收通道接收用于传送到采样电路的模拟信号。 当诊断通道被选择用于与采样电路耦合时，诊断通道接收用于验证采样电路的数字输出的诊断信号。 阻抗补偿器被配置为基于采样电路的容错范围和选择诊断通道来抵消接收通道的高通道阻抗。
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公开(公告)号：US11368009B2
公开(公告)日：2022-06-21
申请号：US17020086
申请日：2020-09-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sri Navaneethakrishnan Easwaran , Timothy Paul Duryea
IPC: H02H3/00 , H03K17/687 , H04B1/40 , H03F3/45
Abstract: An electronic control unit (ECU) operates between first and second voltage rails and includes an amplifier circuit and a single current sense circuit coupled to carry a signal to a bus pin and to protect the bus pin from both a short to ground and a short to battery. The single current sense circuit includes a switch circuit that passes the signal to the bus pin and a forward current sensing circuit that provides a second current that is proportional to an output current at the bus pin. The forward current sensing circuit causes the second current to be substantially zero when voltage on the bus pin is above a given value. The single current sense circuit also includes a forward current protection circuit and a reverse current switching circuit that receives the second current and closes a connection to the second voltage when the second current is zero.
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公开(公告)号：US20190280472A1
公开(公告)日：2019-09-12
申请号：US15913465
申请日：2018-03-06
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Timothy Paul Duryea
IPC: H02H3/00 , H03K17/687
Abstract: An electronic control unit (ECU) operates between first and second voltage rails and includes an amplifier circuit and a single current sense circuit coupled to carry a signal to a bus pin and to protect the bus pin from both a short to ground and a short to battery. The single current sense circuit includes a switch circuit that passes the signal to the bus pin and a forward current sensing circuit that provides a second current that is proportional to an output current at the bus pin. The forward current sensing circuit causes the second current to be substantially zero when voltage on the bus pin is above a given value. The single current sense circuit also includes a forward current protection circuit and a reverse current switching circuit that receives the second current and closes a connection to the second voltage when the second current is zero.
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Patent Agency Ranking
公开(公告)号：US20240259023A1
公开(公告)日：2024-08-01
申请号：US18635134
申请日：2024-04-15
Applicant: Texas Instruments Incorporated
Inventor： Timothy Paul Duryea
IPC: H03K19/23 , G01R31/317 , H03H7/06 , H03K3/037
CPC classification number: H03K19/23 , G01R31/31712 , H03H7/06 , H03K3/037
Abstract: Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.
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公开(公告)号：US10804691B2
公开(公告)日：2020-10-13
申请号：US15913465
申请日：2018-03-06
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Timothy Paul Duryea
IPC: H02H3/00 , H03K17/687 , H04B1/40 , H03F3/45
Abstract: An electronic control unit (ECU) operates between first and second voltage rails and includes an amplifier circuit and a single current sense circuit coupled to carry a signal to a bus pin and to protect the bus pin from both a short to ground and a short to battery. The single current sense circuit includes a switch circuit that passes the signal to the bus pin and a forward current sensing circuit that provides a second current that is proportional to an output current at the bus pin. The forward current sensing circuit causes the second current to be substantially zero when voltage on the bus pin is above a given value. The single current sense circuit also includes a forward current protection circuit and a reverse current switching circuit that receives the second current and closes a connection to the second voltage when the second current is zero.
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公开(公告)号：US09509325B1
公开(公告)日：2016-11-29
申请号：US14706762
申请日：2015-05-07
Applicant: Texas Instruments Incorporated
Inventor： Timothy Paul Duryea , Vaibhav Garg
CPC classification number: H03M1/0607 , H03K19/0005 , H03M1/1076 , H03M1/122 , H03M1/1245 , H03M1/44
Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.
Abstract translation: 本公开描述了一种在模数转换器中使用的通道选择器，其具有用于将模拟输入转换为容错范围内的数字输出的采样电路。 信道选择器包括接收信道，诊断信道和阻抗补偿器。 当接收通道被选择用于与采样电路耦合时，接收通道接收用于传送到采样电路的模拟信号。 当诊断通道被选择用于与采样电路耦合时，诊断通道接收用于验证采样电路的数字输出的诊断信号。 阻抗补偿器被配置为基于采样电路的容错范围和选择诊断通道来抵消接收通道的高通道阻抗。
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公开(公告)号：US20160329904A1
公开(公告)日：2016-11-10
申请号：US14706762
申请日：2015-05-07
Applicant: Texas Instruments Incorporated
Inventor： Timothy Paul Duryea , Vaibhav Garg
CPC classification number: H03M1/0607 , H03K19/0005 , H03M1/1076 , H03M1/122 , H03M1/1245 , H03M1/44
Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.
Abstract translation: 本公开描述了一种在模数转换器中使用的通道选择器，其具有用于将模拟输入转换为容错范围内的数字输出的采样电路。 信道选择器包括接收信道，诊断信道和阻抗补偿器。 当接收通道被选择用于与采样电路耦合时，接收通道接收用于传送到采样电路的模拟信号。 当诊断通道被选择用于与采样电路耦合时，诊断通道接收用于验证采样电路的数字输出的诊断信号。 阻抗补偿器被配置为基于采样电路的容错范围和选择诊断通道来抵消接收通道的高通道阻抗。
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公开(公告)号：US12236177B2
公开(公告)日：2025-02-25
申请号：US17586516
申请日：2022-01-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lawrence James Gewax , Timothy Paul Duryea
IPC: G06F30/33 , G06F30/327 , G06F30/367 , G06F30/398 , G06F119/02
Abstract: One example includes a method for validating a circuit design. The method includes providing a set of coded rules. Each of the coded rules can define conditions for circuit cells to qualify the circuit design as being radiation-hardened. The method also includes accessing a circuit design netlist associated with the circuit design from a circuit design database. The method also includes evaluating each of the circuit cells in the circuit design netlist with respect to each of the coded rules. The method further includes providing a circuit evaluation report comprising an indication of failure of a set of the circuit cells with respect to one or more of the coded rules in response to the evaluation.
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