公开(公告)号：US12087639B2

公开(公告)日：2024-09-10

申请号：US17883898

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7834 ,  H01L29/7851

摘要： A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

公开(公告)号：US20230260843A1

公开(公告)日：2023-08-17

申请号：US18306855

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/762 ,  H01L21/308

CPC分类号： H01L21/823431 ,  H01L29/6681 ,  H01L27/0886 ,  H01L21/76232 ,  H01L21/3081 ,  H01L21/823481

摘要： A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

公开(公告)号：US11670552B2

公开(公告)日：2023-06-06

申请号：US17239965

申请日：2021-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308 ,  H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

摘要： A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

公开(公告)号：US11121255B2

公开(公告)日：2021-09-14

申请号：US16872235

申请日：2020-05-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chii-Horng Li ,  Chih-Shan Chen ,  Roger Tai ,  Yih-Ann Lin ,  Yen-Ru Lee ,  Tzu-Ching Lin

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

摘要： A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

公开(公告)号：US10923565B2

公开(公告)日：2021-02-16

申请号：US16144642

申请日：2018-09-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yih-Ann Lin ,  Yen-Ming Chen

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/10 ,  H01L21/768 ,  H01L21/764

摘要： In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

公开(公告)号：US10763366B2

公开(公告)日：2020-09-01

申请号：US16654906

申请日：2019-10-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chii-Horng Li ,  Chih-Shan Chen ,  Roger Tai ,  Yih-Ann Lin ,  Yen-Ru Lee ,  Tzu-Ching Lin

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

摘要： A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

公开(公告)号：US20240363431A1

公开(公告)日：2024-10-31

申请号：US18766881

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7834 ,  H01L29/7851

摘要： A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

公开(公告)号：US11901408B2

公开(公告)日：2024-02-13

申请号：US17175831

申请日：2021-02-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yih-Ann Lin ,  Yen-Ming Chen

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/10 ,  H01L21/768 ,  H01L21/764

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76897 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/10 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

摘要： In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

公开(公告)号：US11495501B2

公开(公告)日：2022-11-08

申请号：US17169060

申请日：2021-02-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/08

摘要： A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

公开(公告)号：US20210159123A1

公开(公告)日：2021-05-27

申请号：US17169060

申请日：2021-02-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/08

摘要： A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.