公开(公告)号：US12278287B2

公开(公告)日：2025-04-15

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US12249640B2

公开(公告)日：2025-03-11

申请号：US18524417

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US12132091B2

公开(公告)日：2024-10-29

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Ziwei Fang ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/823431 ,  H01L21/823443 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US12100745B2

公开(公告)日：2024-09-24

申请号：US18305636

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/7851 ,  H01L27/0886

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

公开(公告)号：US20240097010A1

公开(公告)日：2024-03-21

申请号：US18524417

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US11923367B2

公开(公告)日：2024-03-05

申请号：US17870964

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

公开(公告)号：US11862713B2

公开(公告)日：2024-01-02

申请号：US17815857

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L29/165

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20230261070A1

公开(公告)日：2023-08-17

申请号：US18305636

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823475 ,  H01L21/823431 ,  H01L29/7851 ,  H01L27/0886

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

公开(公告)号：US20230077541A1

公开(公告)日：2023-03-16

申请号：US18053546

申请日：2022-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yasutoshi Okuno ,  Fu-Ting Yen ,  Teng-Chun Tsai ,  Ziwei Fang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

公开(公告)号：US11594633B2

公开(公告)日：2023-02-28

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.