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公开(公告)号：US20240032309A1
公开(公告)日：2024-01-25
申请号：US18479836
申请日：2023-10-03
发明人： Hung-Li Chiang , Jung-Piao Chiu , Tzu-Chiang Chen , Yu-Sheng Chen , Xinyu BAO
CPC分类号： H10B63/24 , H10N70/021 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8822 , H10N70/8825 , H10N70/8828
摘要： A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.
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公开(公告)号：US20220415968A1
公开(公告)日：2022-12-29
申请号：US17669313
申请日：2022-02-10
发明人： Chien-Min Lee , Cheng-Hsien Wu , Cheng-Chun Chang , Elia Ambrosi , Hengyuan Lee , Ying-Yu Chen , Xinyu BAO , Tung-Ying Lee
摘要： An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
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公开(公告)号：US20220286118A1
公开(公告)日：2022-09-08
申请号：US17736081
申请日：2022-05-03
发明人： Win-San Khwa , Jui-Jen Wu , Jen-Chieh Liu , Elia Ambrosi , Xinyu BAO , Meng-Fan Chang
摘要： A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.
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公开(公告)号：US20220285435A1
公开(公告)日：2022-09-08
申请号：US17362979
申请日：2021-06-29
发明人： Chien-Min Lee , Ming-Yuan Song , Yen-Lin Huang , Shy-Jay Lin , Tung-Ying Lee , Xinyu BAO
摘要： Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
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公开(公告)号：US20240215262A1
公开(公告)日：2024-06-27
申请号：US18601994
申请日：2024-03-11
发明人： Chien-Min Lee , Ming-Yuan Song , Yen-Lin Huang , Shy-Jay Lin , Tung-Ying Lee , Xinyu BAO
CPC分类号： H10B61/22 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , H10N52/00 , H10N52/01 , H10N52/80
摘要： Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
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公开(公告)号：US20240040802A1
公开(公告)日：2024-02-01
申请号：US18152770
申请日：2023-01-11
发明人： Cheng-Hsien Wu , Chen-Feng Hsu , Chien-Min Lee , Tung-Ying Lee , Xinyu BAO , Elia Ambrosi , Hengyuan Lee
IPC分类号： H10B63/00
摘要： A memory device includes a substrate, a bottom electrode disposed over the substrate, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer. The selector layer is an oxygen-doped chalcogenide based film, and an oxygen content of the selector layer is about 10 at % or less.
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公开(公告)号：US20240016072A1
公开(公告)日：2024-01-11
申请号：US17859013
申请日：2022-07-07
发明人： Hengyuan Lee , Yu-Sheng Chen , Cheng-Chun Chang , Xinyu BAO
CPC分类号： H01L45/126 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： A memory cell includes a bottom electrode, a thermal preservation layer, a first dielectric layer, a variable resistance layer, and a top electrode. The bottom electrode includes a first electrode and a second electrode spatially separated from the first electrode. The thermal preservation layer is partially sandwiched between the first electrode and the second electrode. The first dielectric layer laterally surrounds the bottom electrode and the thermal preservation layer. The variable resistance layer is disposed on the second electrode, the thermal preservation layer, and the first dielectric layer. The top electrode is disposed on the variable resistance layer.
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公开(公告)号：US20240015988A1
公开(公告)日：2024-01-11
申请号：US18472235
申请日：2023-09-22
发明人： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu BAO , Hengyuan Lee , Ying-Yu Chen
CPC分类号： H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
摘要： A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US20230386573A1
公开(公告)日：2023-11-30
申请号：US17826180
申请日：2022-05-27
发明人： Elia Ambrosi , Cheng-Hsien Wu , Hengyuan Lee , Chien-Min Lee , Xinyu BAO
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C2213/72
摘要： First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.
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公开(公告)号：US20230008947A1
公开(公告)日：2023-01-12
申请号：US17666553
申请日：2022-02-08
发明人： Hengyuan Lee , Cheng-Hsien Wu , Yu-Sheng Chen , Chien-Min Lee , Xinyu BAO
IPC分类号： G11C13/00
摘要： A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.
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