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1.发明申请SYSTEM AND METHOD FOR WIRELESS AND DYNAMIC INTRA-PROCESS MEASUREMENT OF INTEGRATED CIRCUIT PARAMETERS 有权集成电路参数的无线和动态内部过程测量系统与方法公开(公告)号：US20090240452A1
公开(公告)日：2009-09-24
申请号：US12053705
申请日：2008-03-24
申请人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D.B. Hall , Anthony J. Perri , Sebastian T. Ventrone
发明人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D.B. Hall , Anthony J. Perri , Sebastian T. Ventrone
IPC分类号： G01R23/16
CPC分类号： H04Q9/00 , H01L22/12 , H01L22/14 , H01L22/26 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.
摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 这些实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。
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2.发明授权System and method for wireless and dynamic intra-process measurement of integrated circuit parameters 有权集成电路参数的无线和动态过程内测量的系统和方法公开(公告)号：US08239811B2
公开(公告)日：2012-08-07
申请号：US12053705
申请日：2008-03-24
申请人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D. B. Hall , Anthony J. Perri , Sebastian T. Ventrone
发明人： Theodoros E. Anemikos , Phillip L. Corson , Mete Erturk , Ezra D. B. Hall , Anthony J. Perri , Sebastian T. Ventrone
CPC分类号： H04Q9/00 , H01L22/12 , H01L22/14 , H01L22/26 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.
摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。
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3.发明申请METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效通过调节选择性电压激活切割点来优化功率的方法公开(公告)号：US20090228843A1
公开(公告)日：2009-09-10
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.
摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。 该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。 然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。
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公开(公告)号：US09429619B2
公开(公告)日：2016-08-30
申请号：US13564337
申请日：2012-08-01
IPC分类号： G06F19/00 , G01R31/28 , G05B19/418 , G01R31/317
CPC分类号： G01R31/2894 , G01R31/2855 , G01R31/2868 , G01R31/287 , G01R31/2879 , G01R31/31718 , G05B19/41875 , Y02P90/14 , Y02P90/265
摘要： Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
摘要翻译： 方法和系统通过将制造后的集成电路器件分类为相对较慢的集成电路器件和相对较快的集成电路器件来将集成电路器件分类到不同的电压仓中来优化集成电路设计中的功率利用。 方法和系统为每个电压仓建立一个二进制特定的可靠性测试过程，并使用测试仪测试集成电路器件。 这允许方法和系统将不合格的集成电路设备中的缺陷识别为相应电压箱的专用集成电路可靠性测试过程。 所述方法和系统移除集成电路器件中的有缺陷的集成电路器件，以便只允许无故障的集成电路器件保持并向客户提供无缺陷的集成电路器件。
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5.发明授权System and method to optimize semiconductor power by integration of physical design timing and product performance measurements 有权通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法公开(公告)号：US07877714B2
公开(公告)日：2011-01-25
申请号：US12038320
申请日：2008-02-27
申请人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
摘要翻译： 提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。 该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。
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公开(公告)号：US20130113514A1
公开(公告)日：2013-05-09
申请号：US13288269
申请日：2011-11-03
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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公开(公告)号：US08421495B1
公开(公告)日：2013-04-16
申请号：US13288269
申请日：2011-11-03
IPC分类号： H03K19/003
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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8.发明授权Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point 失效通过调整选择性电压分档切割点来优化集成电路设计的功耗的方法公开(公告)号：US07810054B2
公开(公告)日：2010-10-05
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast identically designed integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests operating speeds and power consumption levels of the identically designed integrated circuit devices. Then, the method adjusts the initial operating speed cut point to a final operating speed cut point based on the testing, to minimize the maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast integrated circuit devices.
摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路器件和相对较快的集成电路器件。 该方法选择初始操作速度切换点以使相对较慢的集成电路器件和相对快速的相同设计的集成电路器件的最大功耗水平最小化。 该方法然后使用集成电路设计制造集成电路器件，并测试相同设计的集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始操作速度切换点调整到最终操作速度切割点，以使相对较慢的集成电路器件和相对快速的集成电路器件的最大功耗水平最小化。
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9.发明申请Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit 审中-公开具有省电输入输出电路的集成电路的设计结构和测试这种集成电路的方法公开(公告)号：US20090115447A1
公开(公告)日：2009-05-07
申请号：US11933646
申请日：2007-11-01
IPC分类号： H03K19/003
CPC分类号： G06F17/505 , G01R31/3016 , G01R33/072 , G06F2217/14
摘要： A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state.
摘要翻译： 一种用于集成电路的设计结构，其包括能够在任何预测的I / O干扰事件期间稳定I / O状态的输入/输出（I / O）状态保存电路。 I / O状态保存电路包括布置在多个相应I / O接收器的输出端与集成电路的内部数字，模拟或混合信号电路之间的多个透明锁存器。 透明锁存器通过公共控制信号在通过模式和状态保存模式之间转换。 在预期的例如预测的I / O信号干扰发生事件中，透明锁存器被设置为状态保存模式。 因此，在干扰事件期间，透明锁存器的输出保持稳定和无毛刺，这确保了集成电路的内部逻辑不会失去状态。
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10.发明授权Design structure for monitoring cross chip delay variation on a semiconductor device 失效用于监测半导体器件上的跨芯片延迟变化的设计结构公开(公告)号：US07487487B1
公开(公告)日：2009-02-03
申请号：US12060488
申请日：2008-04-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a “schmoo plot” by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.
摘要翻译： 一种用于监控半导体电路性能的设计结构，例如芯片上的电路延迟。 该设计结构可以包括时钟源和多个处理监视器。 设计结构可用于通过改变时钟源的频率来构建“schmoo图”，以确定芯片上各处的处理监视器的延迟。
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