利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

28 条记录 (耗时 0.026 秒)

    MRAM device and fabrication method thereof
    2.
    发明授权
    MRAM device and fabrication method thereof 有权
    MRAM器件及其制造方法

    公开(公告)号：US08884386B2

    公开(公告)日：2014-11-11

    申请号：US13364881

    申请日：2012-02-02

    申请人： Tien-Wei Chiang ,  Chwen Yu ,  Ya-Chen Kao

    发明人： Tien-Wei Chiang ,  Chwen Yu ,  Ya-Chen Kao

    IPC分类号： H01L29/82

    CPC分类号： H01L27/222 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01L43/08

    摘要： A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device.

    摘要翻译： 提供了一种磁阻随机存取存储器（MRAM）装置及其制造方法。 MRAM器件包括磁性钉扎层，用作自由层的复合GMR结构以及分离钉扎和GMR层的非磁性阻挡层。 提供阻挡层以减少自由层和GMR结构的磁耦合，以及提供用于在装置中保持二进制数据（0或1）的电阻状态（高或低）。 GMR结构提供了用于设置/清除存储器功能的物理电极连接，其与用于存储器件的读取功能的物理电极连接分开。

    MRAM Device and Fabrication Method Thereof
    4.
    发明申请
    MRAM Device and Fabrication Method Thereof 有权
    MRAM器件及其制造方法

    公开(公告)号：US20130200475A1

    公开(公告)日：2013-08-08

    申请号：US13364881

    申请日：2012-02-02

    申请人： Tien-Wei Chiang ,  Chwen Yu ,  Ya-Chen Kao

    发明人： Tien-Wei Chiang ,  Chwen Yu ,  Ya-Chen Kao

    IPC分类号： H01L29/82

    CPC分类号： H01L27/222 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01L43/08

    摘要： A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device.

    摘要翻译： 提供了一种磁阻随机存取存储器（MRAM）装置及其制造方法。 MRAM器件包括磁性钉扎层，用作自由层的复合GMR结构以及分离钉扎和GMR层的非磁性阻挡层。 提供阻挡层以减少自由层和GMR结构的磁耦合，以及提供用于在装置中保持二进制数据（0或1）的电阻状态（高或低）。 GMR结构提供了用于设置/清除存储器功能的物理电极连接，其与用于存储器件的读取功能的物理电极连接分开。

    SPIN TORQUE TRANSFER MAGNETIC TUNNEL JUNCTION STRUCTURE
    8.
    发明申请
    SPIN TORQUE TRANSFER MAGNETIC TUNNEL JUNCTION STRUCTURE 有权
    旋转转矩磁铁隧道结构

    公开(公告)号：US20100258886A1

    公开(公告)日：2010-10-14

    申请号：US12422579

    申请日：2009-04-13

    申请人： Yu-Jen Wang ,  Ya-Chen Kao ,  Chun-Jung Lin

    发明人： Yu-Jen Wang ,  Ya-Chen Kao ,  Chun-Jung Lin

    IPC分类号： H01L29/82 ,  H01L21/00

    CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/12

    摘要： The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.

    摘要翻译： 本公开提供一种半导体存储器件。 该器件包括在半导体衬底上的底部电极; 设置在底部电极上的反铁磁层; 设置在反铁磁层上的钉扎层; 设置在被钉扎层上的阻挡层; 设置在阻挡层上的第一铁磁层; 设置在所述第一铁磁层上的缓冲层，所述缓冲层包括钽; 设置在所述缓冲层上的第二铁磁层; 以及设置在第二铁磁层上的顶电极。

    Poly etching solution to improve silicon trench for low STI profile
    9.
    发明授权
    Poly etching solution to improve silicon trench for low STI profile 有权
    Poly蚀刻解决方案，以改善硅沟槽的低STI特性

    公开(公告)号：US06649489B1

    公开(公告)日：2003-11-18

    申请号：US10366207

    申请日：2003-02-13

    申请人： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

    发明人： Li-Wen Chang ,  Hung-Cheng Sung ,  Der-Shin Shyu ,  Han-Ping Chen ,  Chen-Ming Huang ,  Ya-Chen Kao

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232

    摘要： A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

    摘要翻译： 描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。 衬底上设置介电层，并在电介质层上设置多晶硅层。 形成浅沟槽，其延伸穿过多晶硅和电介质层进入衬底。 绝缘材料用于填充沟槽，然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。 沉积保形缓冲层，其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。 将缓冲层回蚀刻以暴露绝缘层，并且通过等离子体蚀刻去除多晶硅。 由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽，从而增加蚀刻工艺窗口。

    REVERSE CONNECTION MTJ CELL FOR STT MRAM
    10.
    发明申请
    REVERSE CONNECTION MTJ CELL FOR STT MRAM 有权
    反向连接用于STT MRAM的MTJ单元

    公开(公告)号：US20110122674A1

    公开(公告)日：2011-05-26

    申请号：US12626092

    申请日：2009-11-25

    申请人： CHUN-JUNG LIN ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    发明人： CHUN-JUNG LIN ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    IPC分类号： G11C11/22 ,  H01L29/82 ,  H01L21/28

    CPC分类号： H01L43/08 ,  G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/12

    摘要： Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

    摘要翻译： 本文公开了用于MRAM的反向连接STT MTJ元件的装置和方法，以在将MTJ元件的磁化从平行方向切换到反平行方向时克服源退化效应。 具有反向连接MTJ元件的MRAM的存储单元包括具有源极，栅极和漏极的开关器件和具有自由层，固定层和绝缘体层的反向连接MTJ器件， 自由层和固定层。 反连接MTJ器件的自由层连接到开关器件的漏极，固定层连接到位线（BL）。 反向连接MTJ设备将由源退化效应引起的存储器单元的较低IMTJ能力应用于较不严格的IMTJ（AP-> P），同时为更苛刻的IMTJ（P-> AP）保持较高的IMTJ能力。