公开(公告)号：US11670713B2

公开(公告)日：2023-06-06

申请号：US17884599

申请日：2022-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yen Feng ,  Chen-An Kuo ,  Ching-Wei Teng ,  Po-Chun Lai

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/285 ,  H01L21/74 ,  H01L29/45

CPC classification number: H01L29/7816 ,  H01L21/28518 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/45 ,  H01L29/66681

Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

公开(公告)号：US20220384638A1

公开(公告)日：2022-12-01

申请号：US17884599

申请日：2022-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yen Feng ,  Chen-An Kuo ,  Ching-Wei Teng ,  Po-Chun Lai

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/45 ,  H01L21/285 ,  H01L21/74

Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

公开(公告)号：US11798998B2

公开(公告)日：2023-10-24

申请号：US17895042

申请日：2022-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/76 ,  H01L31/062 ,  H01L29/94 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7816

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US20220406902A1

公开(公告)日：2022-12-22

申请号：US17895042

申请日：2022-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/40 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US20200266267A1

公开(公告)日：2020-08-20

申请号：US16358556

申请日：2019-03-19

Applicant: United Microelectronics Corp.

Inventor： HSIANG-HUA HSU ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L21/265

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

公开(公告)号：US11791386B2

公开(公告)日：2023-10-17

申请号：US17895054

申请日：2022-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/76 ,  H01L31/062 ,  H01L29/94 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7816

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US11616139B2

公开(公告)日：2023-03-28

申请号：US17224108

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yen Feng ,  Chen-An Kuo ,  Ching-Wei Teng ,  Po-Chun Lai

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/285 ,  H01L21/74 ,  H01L29/45

Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

公开(公告)号：US11195905B2

公开(公告)日：2021-12-07

申请号：US16358556

申请日：2019-03-19

Applicant: United Microelectronics Corp.

Inventor： Hsiang-Hua Hsu ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/778

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

公开(公告)号：US20210351294A1

公开(公告)日：2021-11-11

申请号：US16896233

申请日：2020-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Hsin Huang ,  Chen-An Kuo ,  Po-Chun Lai

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. A top of the isolation structure includes a flat surface, and a bottom of the isolation structure includes a curved surface.

公开(公告)号：US11817496B2

公开(公告)日：2023-11-14

申请号：US17515573

申请日：2021-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Hsin Huang ,  Chen-An Kuo ,  Po-Chun Lai

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66681

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. The isolation structure includes a curved bottom surface.