公开(公告)号：US20150249158A1

公开(公告)日：2015-09-03

申请号：US14194957

申请日：2014-03-03

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Hua-Kuo Lee ,  Ching-Long Tsai ,  Chi Ren ,  Cheng-Yuan Hsu

IPC: H01L29/788 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/42328

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，第一栅极结构，第二栅电极，第三栅电极和保护层。 第一栅极结构包括设置在衬底上的第一栅极电极和覆盖第一栅电极的第一栅极电介质。 第二栅电极设置在第一栅电极上并与第一栅极电隔离。 第一栅极结构具有相对于第二栅电极的延伸部分。 第三栅电极设置成与第一栅电极和第二栅电极相邻并与之隔离。 第三栅极在保护层的下表面和第一栅极结构的延伸部分的上表面之间具有延伸部分。

公开(公告)号：US20150014761A1

公开(公告)日：2015-01-15

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHEN CHEN ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng ,  PING LIU

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US09786489B1

公开(公告)日：2017-10-10

申请号：US15461486

申请日：2017-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming Sheng Xu ,  Ching-Long Tsai ,  Hua-Kuo Lee ,  Guangjun Huang

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L2224/45147 ,  H01L2924/01029 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335

Abstract: A method of cleaning post-etch residues on a copper line includes providing a copper line which is divided into a first region and a second region. A dielectric layer is formed on the copper line. After that, the dielectric layer is etched to form openings in the dielectric layer. A number of openings within the first region is more than a number of openings in the second region. During the etching process, a potential difference is formed between the first region and the second region of the copper line. Finally, the dielectric layer and the copper line are cleaned by a solution with a PH value. The PH value has a special relation with the potential difference.

公开(公告)号：US09431256B2

公开(公告)日：2016-08-30

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  Zhen Chen ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng ,  Ping Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US08921913B1

公开(公告)日：2014-12-30

申请号：US13923374

申请日：2013-06-21

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yuan Hsu ,  Zhaobing Li ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。

公开(公告)号：US20140377945A1

公开(公告)日：2014-12-25

申请号：US13923374

申请日：2013-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHAOBING LI ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。