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    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210249357A1

    公开(公告)日：2021-08-12

    申请号：US16786919

    申请日：2020-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC: H01L23/544 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

    Fabricating method of transistors without dishing occurred during CMP process
    7.
    发明授权
    Fabricating method of transistors without dishing occurred during CMP process 有权

    公开(公告)号：US11257711B1

    公开(公告)日：2022-02-22

    申请号：US17023391

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02

    Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

    FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS
    8.
    发明申请
    FABRICATING METHOD OF TRANSISTORS WITHOUT DISHING OCCURRED DURING CMP PROCESS 有权

    公开(公告)号：US20220084878A1

    公开(公告)日：2022-03-17

    申请号：US17023391

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3105

    Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

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