公开(公告)号：US20170213818A1

公开(公告)日：2017-07-27

申请号：US15481444

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

公开(公告)号：US09660072B2

公开(公告)日：2017-05-23

申请号：US14188645

申请日：2014-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided.

公开(公告)号：US20160043216A1

公开(公告)日：2016-02-11

申请号：US14454739

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。

公开(公告)号：US20150221634A1

公开(公告)日：2015-08-06

申请号：US14685588

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，形成在衬底中的栅极的相应两侧处的漏极区域和源极区域，形成在漏极区域中的至少第一掺杂区域，以及至少第一 其中形成有第一掺杂区。 源区和漏区包括第一导电类型，第一掺杂区和第一阱包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US08896024B1

公开(公告)日：2014-11-25

申请号：US13940081

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/87

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a first and a second well region adjacent to each other, a first and a second doped region disposed in the first well region, a fourth and a fifth doped region disposed in the second well region, and a third doped region disposed in the first region and extending into the second well region. The second doped region is disposed between the first and the third doped regions, forming a diode with the first doped region, forming, together with the first well region and the second well region, a first bipolar junction transistor (BJT) electrically connecting to the diode, and having no contact window disposed thereon. The fourth doped region is disposed between the third and the fifth doped regions, forming a second BJT with the second well region and the first well region.

Abstract translation: 提供一种静电放电（ESD）保护结构，其包括彼此相邻的第一和第二阱区，设置在第一阱区中的第一和第二掺杂区，设置在第二阱区中的第四和第五掺杂区 以及设置在第一区域中并延伸到第二阱区域中的第三掺杂区域。 第二掺杂区域设置在第一和第三掺杂区域之间，形成具有第一掺杂区域的二极管，与第一阱区域和第二阱区域一起形成电连接到第一掺杂区域的第一双极结型晶体管（BJT） 二极管，并且没有布置在其上的接触窗口。 第四掺杂区域设置在第三和第五掺杂区域之间，与第二阱区域和第一阱区域形成第二BJT。

公开(公告)号：US20160204598A1

公开(公告)日：2016-07-14

申请号：US14594173

申请日：2015-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H02H9/04

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

Abstract translation: 本发明提供一种电连接在高压电力线和低电压电力线之间的ESD保护电路，该ESD保护电路包括双极结型晶体管（BJT）和触发源。 BJT的集电极电连接到高压电力线，并且BJT的发射极和基极电连接到低压电力线。 触发源电连接在BJT的基极和高压电源线之间。

公开(公告)号：US09362420B2

公开(公告)日：2016-06-07

申请号：US13746296

申请日：2013-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L29/861 ,  H01L27/02

CPC classification number: H01L29/861 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0274

Abstract: The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.

Abstract translation: 本发明公开了一种用于静电放电保护的晶体管结构。 该结构包括衬底，掺杂阱，第一掺杂区，第二掺杂区和第三掺杂区。 掺杂阱设置在衬底中并且具有第一导电类型。 第一掺杂区域设置在衬底中，由掺杂阱包围并具有第一导电类型。 第二掺杂区域设置在衬底中，被掺杂阱覆盖并具有第二导电类型。 第三掺杂区域设置在衬底中，被掺杂阱包围并具有第二导电类型。 间隙设置在第一掺杂区和第二掺杂区之间。

公开(公告)号：US20160035823A1

公开(公告)日：2016-02-04

申请号：US14446344

申请日：2014-07-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0619 ,  H01L29/0692 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，在栅极的两个侧面处形成在衬底中的源极区和形成在衬底中的源极区，形成在衬底中的第一阱区，以及形成的多个第一掺杂岛 在源区。 漏区和源极区包括第一导电性，第一阱区和第一掺杂岛包括第二导电性。 源极区形成在第一阱区中，并且第一掺杂岛与第一阱区间隔开。

公开(公告)号：US09041110B2

公开(公告)日：2015-05-26

申请号：US13848069

申请日：2013-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L29/78 ,  H01L27/02 ,  H01L29/08 ,  H01L23/60

CPC classification number: H01L27/0266 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，形成在衬底中的栅极的相应两侧处的漏极区域和源极区域，形成在漏极区域中的至少第一掺杂区域，以及至少第一 其中形成有第一掺杂区。 源区和漏区包括第一导电类型，第一掺杂区和第一阱包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20140203367A1

公开(公告)日：2014-07-24

申请号：US13746296

申请日：2013-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L29/861 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0274

Abstract: The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.

Abstract translation: 本发明公开了一种用于静电放电保护的晶体管结构。 该结构包括衬底，掺杂阱，第一掺杂区，第二掺杂区和第三掺杂区。 掺杂阱设置在衬底中并且具有第一导电类型。 第一掺杂区域设置在衬底中，由掺杂阱包围并具有第一导电类型。 第二掺杂区域设置在衬底中，被掺杂阱覆盖并具有第二导电类型。 第三掺杂区域设置在衬底中，被掺杂阱包围并具有第二导电类型。 间隙设置在第一掺杂区和第二掺杂区之间。