公开(公告)号：US20240178137A1

公开(公告)日：2024-05-30

申请号：US18108024

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： XINGXING CHEN ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L23/528 ,  H01L23/522 ,  H01Q1/38

CPC classification number: H01L23/528 ,  H01L23/5227 ,  H01Q1/38

Abstract: A method for determining antenna rule for a radio-frequency (RF) device includes the steps of forming a gate structure on a substrate, forming a source/drain region adjacent to the gate structure, forming a first metal routing on the source/drain region, and then forming a second metal routing on the gate structure. Preferably, a sum of an area of the first metal routing and an area of the second metal routing divided by an area of the gate structure is less than a ratio.

公开(公告)号：US20240234350A9

公开(公告)日：2024-07-11

申请号：US17989633

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L25/16 ,  H01L27/1203 ,  H01L28/90 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

公开(公告)号：US20230094739A1

公开(公告)日：2023-03-30

申请号：US17510392

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  Sheng Zhang ,  XINGXING CHEN ,  Chien-Kee Pang

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/16

Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

公开(公告)号：US20230071686A1

公开(公告)日：2023-03-09

申请号：US17987766

申请日：2022-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN ,  CHAO JIN

IPC: H01G4/38 ,  H01L49/02 ,  H01L23/522 ,  H01G4/008 ,  H01L21/321 ,  H01L27/01 ,  H01L23/528 ,  H01L21/288

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

公开(公告)号：US20190051666A1

公开(公告)日：2019-02-14

申请号：US15691757

申请日：2017-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Shen Li ,  XIAOYUAN ZHI ,  XINGXING CHEN ,  Ching-Yang Wen

IPC: H01L27/12 ,  H01L23/48 ,  H01L21/84 ,  H01L21/768 ,  H01L21/683

Abstract: A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element.

公开(公告)号：US20240266393A1

公开(公告)日：2024-08-08

申请号：US18119797

申请日：2023-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  XINGXING CHEN ,  ZHUONA MA ,  HUI LIU

IPC: H01L29/06 ,  H01L21/308 ,  H01L27/12 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/3086 ,  H01L27/1203 ,  H01L29/1604

Abstract: A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.

公开(公告)号：US20240136312A1

公开(公告)日：2024-04-25

申请号：US17989633

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L25/16 ,  H01L27/1203 ,  H01L28/90 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

公开(公告)号：US20210313116A1

公开(公告)日：2021-10-07

申请号：US16854887

申请日：2020-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN ,  CHAO JIN

IPC: H01G4/38 ,  H01L49/02 ,  H01L23/522 ,  H01L21/288 ,  H01L21/321 ,  H01L27/01 ,  H01L23/528 ,  H01G4/008

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.