公开(公告)号：US20160141383A1

公开(公告)日：2016-05-19

申请号：US15003813

申请日：2016-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L29/51 ,  H01L29/78 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 在所述基板上的第一拉伸介电层; 第一拉伸介电层中的金属栅极; 第一拉伸介电层上的第二拉伸电介质层; 以及第一拉伸介电层和第二拉伸介电层中的接触塞。 优选地，接触塞的顶表面与第二拉伸介电层的顶表面均匀，并且第二拉伸介电层的碳含量大于第一拉伸介电层的碳含量。

公开(公告)号：US20200258771A1

公开(公告)日：2020-08-13

申请号：US16858698

申请日：2020-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/522

Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.

公开(公告)号：US09281238B2

公开(公告)日：2016-03-08

申请号：US14328717

申请日：2014-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/31

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating interlayer dielectric (ILD) layer is disclosed. The method includes the steps of first forming a first tensile dielectric layer on a substrate, and then forming a second tensile dielectric layer on the first tensile dielectric layer.

Abstract translation: 公开了一种用于制造层间电介质（ILD）层的方法。 该方法包括以下步骤：首先在衬底上形成第一拉伸电介质层，然后在第一拉伸电介质层上形成第二拉伸电介质层。

公开(公告)号：US20160013098A1

公开(公告)日：2016-01-14

申请号：US14328717

申请日：2014-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L21/768

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating interlayer dielectric (ILD) layer is disclosed. The method includes the steps of first forming a first tensile dielectric layer on a substrate, and then forming a second tensile dielectric layer on the first tensile dielectric layer.

Abstract translation: 公开了一种用于制造层间电介质（ILD）层的方法。 该方法包括以下步骤：首先在衬底上形成第一拉伸电介质层，然后在第一拉伸电介质层上形成第二拉伸电介质层。

公开(公告)号：US11373901B2

公开(公告)日：2022-06-28

申请号：US16858698

申请日：2020-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/522

Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.

公开(公告)号：US10679893B2

公开(公告)日：2020-06-09

申请号：US16121605

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.

公开(公告)号：US20160274570A1

公开(公告)日：2016-09-22

申请号：US14660961

申请日：2015-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lian-Hua Shih ,  Ching-Hsing Hsieh ,  Feng-Chi Chung ,  Chia-Chi Chang ,  Yu-Cheng Lin ,  Sian-Jhu Tsai ,  Meng-Chih Chang ,  Yi-Hui Tseng

IPC: G05B19/4097 ,  G05B15/02

CPC classification number: G05B19/41875 ,  G05B2219/32194 ,  G05B2219/37224 ,  Y02P90/22

Abstract: A method of virtual metrology is disclosed. Process data and measurement values corresponding to a workpiece are collected. The process data and the measurement values are used to establish a conjecture model. A theoretical model corresponding to the workpiece and the conjecture model is used to establish another conjecture model. The another conjecture model is used to establish a virtual metrology value. The virtual metrology value is used to predict properties of a subsequently manufactured workpiece.

Abstract translation: 公开了一种虚拟测量方法。 收集与工件对应的工艺数据和测量值。 过程数据和测量值用于建立猜想模型。 使用对应于工件和推测模型的理论模型来建立另一个推测模型。 另一个猜想模型用于建立虚拟计量学值。 虚拟计量值用于预测随后制造的工件的性能。

公开(公告)号：US20200075395A1

公开(公告)日：2020-03-05

申请号：US16121605

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/522

Abstract: An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.

公开(公告)号：US09564507B2

公开(公告)日：2017-02-07

申请号：US15003813

申请日：2016-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Hui-Shen Shih

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/31 ,  H01L29/51 ,  H01L23/532 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L29/51 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first tensile dielectric layer on the substrate; a metal gate in the first tensile dielectric layer; a second tensile dielectric layer on the first tensile dielectric layer; and a contact plug in the first tensile dielectric layer and the second tensile dielectric layer. Preferably, the top surface of the contact plug is even with the top surface of the second tensile dielectric layer, and a carbon content of the second tensile dielectric layer is greater than the carbon content of the first tensile dielectric layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 在所述基板上的第一拉伸介电层; 第一拉伸介电层中的金属栅极; 第一拉伸介电层上的第二拉伸电介质层; 以及第一拉伸介电层和第二拉伸介电层中的接触塞。 优选地，接触塞的顶表面与第二拉伸介电层的顶表面均匀，并且第二拉伸介电层的碳含量大于第一拉伸介电层的碳含量。