公开(公告)号：US20150249158A1

公开(公告)日：2015-09-03

申请号：US14194957

申请日：2014-03-03

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Hua-Kuo Lee ,  Ching-Long Tsai ,  Chi Ren ,  Cheng-Yuan Hsu

IPC: H01L29/788 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/42328

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，第一栅极结构，第二栅电极，第三栅电极和保护层。 第一栅极结构包括设置在衬底上的第一栅极电极和覆盖第一栅电极的第一栅极电介质。 第二栅电极设置在第一栅电极上并与第一栅极电隔离。 第一栅极结构具有相对于第二栅电极的延伸部分。 第三栅电极设置成与第一栅电极和第二栅电极相邻并与之隔离。 第三栅极在保护层的下表面和第一栅极结构的延伸部分的上表面之间具有延伸部分。

公开(公告)号：US20150014761A1

公开(公告)日：2015-01-15

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHEN CHEN ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng ,  PING LIU

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US20140183614A1

公开(公告)日：2014-07-03

申请号：US13733147

申请日：2013-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHAOBING LI ,  Cheng-Yuan Hsu ,  CHI REN

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a first gate, a shallow trench isolation (STI) and a third gate. The first gate is disposed on the semiconductor substrate, and the first gate partially overlaps the third gate and the shallow trench isolation. Furthermore, the third gate is disposed in a shallow trench isolation, and the third gate includes at least a protrusion.

Abstract translation: 提供半导体器件。 半导体器件包括半导体衬底，至少第一栅极，浅沟槽隔离（STI）和第三栅极。 第一栅极设置在半导体衬底上，第一栅极部分地与第三栅极重叠并且浅沟槽隔离。 此外，第三栅极设置在浅沟槽隔离中，并且第三栅极至少包括突起。

公开(公告)号：US20150056768A1

公开(公告)日：2015-02-26

申请号：US14516592

申请日：2014-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  CHI Ren ,  Tzeng-Fei Wen

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7882

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括以下步骤：在半导体衬底上依次形成玛瑙电介质层和第一栅极层，其中栅介电层位于第一栅层和半导体衬底之间; 在所述第一栅极层中形成至少一个开口; 在所述半导体衬底上共形形成第一电介质层，其中所述第一电介质层覆盖所述第一栅极层; 以及形成填充所述开口并与所述第一栅极层重叠的第二栅极层。

公开(公告)号：US09431256B2

公开(公告)日：2016-08-30

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  Zhen Chen ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng ,  Ping Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US09117847B2

公开(公告)日：2015-08-25

申请号：US14516592

申请日：2014-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  Chi Ren ,  Tzeng-Fei Wen

IPC: H01L21/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L21/266

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7882

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer.

Abstract translation: 公开了制造半导体器件的方法。 该方法包括以下步骤：在半导体衬底上依次形成玛瑙电介质层和第一栅极层，其中栅介电层位于第一栅层和半导体衬底之间; 在所述第一栅极层中形成至少一个开口; 在所述半导体衬底上共形形成第一电介质层，其中所述第一电介质层覆盖所述第一栅极层; 以及形成填充所述开口并与所述第一栅极层重叠的第二栅极层。

公开(公告)号：US20150115346A1

公开(公告)日：2015-04-30

申请号：US14062905

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: A semiconductor memory device includes a substrate, shallow trench isolations protruding from the substrate, a floating gate formed conformally on the surface of the recess between each shallow trench isolation, a tunnel layer formed between each floating gate and the substrate, a dielectric layer formed conformally on the floating gates, and a control gate formed on the dielectric layer.

Abstract translation: 半导体存储器件包括衬底，从衬底突出的浅沟槽隔离物，在每个浅沟槽隔离件之间的凹槽表面上共形形成的浮栅，在每个浮置栅极和衬底之间形成的隧道层，保形地形成的电介质层 在浮置栅极上，以及形成在电介质层上的控制栅极。

公开(公告)号：US08921913B1

公开(公告)日：2014-12-30

申请号：US13923374

申请日：2013-06-21

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yuan Hsu ,  Zhaobing Li ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。

公开(公告)号：US20140377945A1

公开(公告)日：2014-12-25

申请号：US13923374

申请日：2013-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHAOBING LI ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。