公开(公告)号：US07724598B1

公开(公告)日：2010-05-25

申请号：US11737654

申请日：2007-04-19

申请人： Vinson Chan ,  Chong H. Lee ,  Binh Ton ,  Thiagaraja Gopalsamy ,  Marcel A. LeBlanc ,  Neville Carvalho

发明人： Vinson Chan ,  Chong H. Lee ,  Binh Ton ,  Thiagaraja Gopalsamy ,  Marcel A. LeBlanc ,  Neville Carvalho

IPC分类号： G11C7/00

CPC分类号： G06F12/0292 ,  G06F12/0623 ,  G06F2212/1048

摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.

摘要翻译： 提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。 宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。 因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。 因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。 控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

公开(公告)号：US09170952B1

公开(公告)日：2015-10-27

申请号：US13338707

申请日：2011-12-28

申请人： Divya Vijayaraghavan ,  Vinson Chan ,  Keith Duwel ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Vinson Chan ,  Keith Duwel ,  Chong H. Lee

IPC分类号： G06F13/00 ,  G06F12/02 ,  G06F12/08 ,  G06F13/12 ,  G06F13/14 ,  G06F11/00 ,  H01L25/00 ,  H04J3/06

CPC分类号： G06F12/0862 ,  G06F13/00 ,  H03K19/17744

摘要： A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.

摘要翻译： 可配置接口包括发射器模块和接收器模块，每个发送器模块和接收器模块被配置为根据至少三个不同的接口标准进行操作。 所述可配置接口还包括接口模块，所述接口模块被配置为确定耦合到所述可配置接口的PMA的物理介质连接（PMA）标准，并基于所述PMA标准激活所述可配置接口的至少一个组件。 在这种安排中，设备接口支持CAUI-4标准。

公开(公告)号：US09531646B1

公开(公告)日：2016-12-27

申请号：US12632744

申请日：2009-12-07

申请人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee ,  Vinson Chan

发明人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee ,  Vinson Chan

IPC分类号： G06F3/00 ,  H04L12/861 ,  G06F5/10

CPC分类号： H04L49/90 ,  G06F5/10

摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.

摘要翻译： 实施例包括可配置的多协议收发器，包括可配置的偏移电路。 在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。 在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。 在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。 在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。 在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。

公开(公告)号：US06970117B1

公开(公告)日：2005-11-29

申请号：US10789406

申请日：2004-02-26

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M9/00 ,  H04L7/02

CPC分类号： H04L7/0054 ,  H03M9/00

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US07984209B1

公开(公告)日：2011-07-19

申请号：US11638150

申请日：2006-12-12

申请人： Vinson Chan ,  Michael Menghui Zheng ,  Chong H. Lee

发明人： Vinson Chan ,  Michael Menghui Zheng ,  Chong H. Lee

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F5/12 ,  G06F2205/126

摘要： Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

摘要翻译： 用于在可能具有一些不同速度的两种不同时钟制式之间对数据进行接口的接口电路包括确定哪个时钟方案更快的能力。 根据哪个时钟状态被发现更快，基线（数据写入和接口电路中的FIFO存储器的数据读取地址之间的标称差）被移位（即，朝向FIFO的满或空状态，如适用的那样） 为什么时钟制度被发现是更快）。 还可以对用于诸如字符插入/删除和溢出/下溢指示的目的的阈值进行调整。 该技术可以允许使用较小的FIFO并减少接口电路的延迟。

公开(公告)号：US07046174B1

公开(公告)日：2006-05-16

申请号：US11147757

申请日：2005-06-07

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H04L7/0331

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US06724328B1

公开(公告)日：2004-04-20

申请号：US10454626

申请日：2003-06-03

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M900

CPC分类号： H04L7/0054 ,  H03M9/00

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US08949493B1

公开(公告)日：2015-02-03

申请号：US12847761

申请日：2010-07-30

申请人： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

发明人： Curt Wortman ,  Chong H. Lee ,  Huy Ngo

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F5/00 ,  G06F13/12 ,  G06M3/00 ,  G11C19/00 ,  G01R31/28 ,  G06F17/50 ,  G06F1/02 ,  G06F7/58 ,  H04L9/00

CPC分类号： H04L25/03866 ,  G06F3/00 ,  G06F5/00 ,  G06F7/58 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/4221 ,  G06F13/4282 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/285 ,  H04L9/00

摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

摘要翻译： 公开了与可配置加扰电路相关的各种结构和方法。 实施例可以被配置为支持多个协议中的一个。 一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。 一些实施例可配置为选择加扰器类型。 一些实施例可配置为适应多个协议特定的加扰多项式之一。 一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。 在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

公开(公告)号：US08462908B2

公开(公告)日：2013-06-11

申请号：US12974949

申请日：2010-12-21

申请人： Ramanand Venkata ,  Chong H. Lee

发明人： Ramanand Venkata ,  Chong H. Lee

IPC分类号： H03D3/24

CPC分类号： H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

摘要翻译： 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。

公开(公告)号：US20110211621A1

公开(公告)日：2011-09-01

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。