公开(公告)号：US07039787B1

公开(公告)日：2006-05-02

申请号：US10984684

申请日：2004-11-09

申请人： Ramanand Venkata ,  Chong H. Lee

发明人： Ramanand Venkata ,  Chong H. Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/4018 ,  H04J3/0608

摘要： Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.

摘要翻译： 用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。 在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。 如果字节对齐电路随后检测到提示可能需要新的或改变的字节对齐的信息，则输出第二状态信号。 然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。 通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

公开(公告)号：US06867616B1

公开(公告)日：2005-03-15

申请号：US10455773

申请日：2003-06-04

申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03D3/24

CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.

摘要翻译： 在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。 这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。 对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

公开(公告)号：US07646217B2

公开(公告)日：2010-01-12

申请号：US11539006

申请日：2006-10-05

申请人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

发明人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

IPC分类号： H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17784

摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

摘要翻译： 在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。 设备上的部分或全部功能块被补充有串行接口。 尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。 这意味着设备功耗的显着降低。 串行接口可以与全局设备时钟（例如PLL）同步工作。 在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口 块将不得不更复杂，因为它们必须能够与外部设备异步操作。

公开(公告)号：US07436210B2

公开(公告)日：2008-10-14

申请号：US11655797

申请日：2007-01-18

申请人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

发明人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： H03K19/173

CPC分类号： G06F13/385

摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

摘要翻译： 在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

公开(公告)号：US07151470B1

公开(公告)日：2006-12-19

申请号：US10969450

申请日：2004-10-20

申请人： Ning Xue ,  Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

发明人： Ning Xue ,  Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC分类号： H03M7/00

CPC分类号： H03M7/04

摘要： A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

摘要翻译： 用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换，例如在64位和66位之间，在24位和26位之间，或在48位和50位之间。 这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的，这些时钟速度全部来自相同的主时钟（可以从接收机实施例中的数据恢复）。 当转换不是设计齿轮箱的最大宽度的转换时，未使用的位将被忽略。 转换器还可以在不同宽度的数据中找到用于对齐目的的填充位，当数据不是设计转换器的最宽时，再次忽略未使用的位。

公开(公告)号：US06888376B1

公开(公告)日：2005-05-03

申请号：US10670845

申请日：2003-09-24

申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1778 ,  H03K19/17796

摘要： A serial interface for a programmable logic device supports a higher physical medium attachment (“PMA”) data rate than the available physical coding sublayer (“PCS”) data rate by using multiple PCS modules, operating in parallel, to support one PMA module. In a channel-based structure, the PMA module is supported by a PCS module in its own channel and at least one PCS module from a second channel. The second channel may include its own PMA module which, if provided, may operate at a lower rate, supportable by the PCS module in that channel. Optionally, two modes are provided. In one mode, two PCS modules in two channels support one higher-speed PMA module in one of the channels. In a second mode, each PCS module supports a PMA module in its own channel, with the higher-speed PMA module constrained to operate at the lower data rate of the PCS module.

摘要翻译： 用于可编程逻辑器件的串行接口通过使用并行操作的多个PCS模块来支持比可用物理编码子层（“PCS”）数据速率更高的物理介质附加（“PMA”）数据速率，以支持一个PMA模块。 在基于通道的结构中，PMA模块由其自身通道中的PCS模块和来自第二通道的至少一个PCS模块支持。 第二通道可以包括其自己的PMA模块，如果提供的话，该模块可以以较低的速率操作，由PCS模块在该通道中支持。 可选地，提供两种模式。 在一种模式下，两个通道中的两个PCS模块在其中一个通道中支持一个更高速的PMA模块。 在第二种模式下，每个PCS模块都支持自己的通道中的PMA模块，而高速PMA模块则被限制在PCS模块的较低数据速率下工作。

公开(公告)号：US07869553B1

公开(公告)日：2011-01-11

申请号：US10923129

申请日：2004-08-20

申请人： Ramanand Venkata ,  Chong H Lee

发明人： Ramanand Venkata ,  Chong H Lee

IPC分类号： H03D3/24

CPC分类号： H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

摘要翻译： 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。

公开(公告)号：US07138837B2

公开(公告)日：2006-11-21

申请号：US10349541

申请日：2003-01-21

申请人： Ramanand Venkata ,  Chong H. Lee ,  Henry Lui

发明人： Ramanand Venkata ,  Chong H. Lee ,  Henry Lui

IPC分类号： H03L7/00

CPC分类号： H03L7/089 ,  H03L2207/50 ,  H04L7/0337

摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal.

摘要翻译： 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。

公开(公告)号：US07046174B1

公开(公告)日：2006-05-16

申请号：US11147757

申请日：2005-06-07

申请人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

发明人： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H04L7/0331

摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

摘要翻译： 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US06963223B2

公开(公告)日：2005-11-08

申请号：US10835081

申请日：2004-04-28

申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC分类号： H03K19/177 ,  H04Q11/04

CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0094

摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.