公开(公告)号：US20230118367A1

公开(公告)日：2023-04-20

申请号：US17504546

申请日：2021-10-19

Applicant: Winbond Electronics Corp.

Inventor： Wen-Chieh Tsai ,  Cheng-Ta Yang ,  Tsung-Wei Lin

IPC: H01L23/528 ,  H01L21/768

Abstract: Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.

公开(公告)号：US12183833B2

公开(公告)日：2024-12-31

申请号：US17592832

申请日：2022-02-04

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B41/49

Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

公开(公告)号：US11876048B2

公开(公告)日：2024-01-16

申请号：US17504546

申请日：2021-10-19

Applicant: Winbond Electronics Corp.

Inventor： Wen-Chieh Tsai ,  Cheng-Ta Yang ,  Tsung-Wei Lin

IPC: H01L21/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816

Abstract: Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.

公开(公告)号：US10896911B2

公开(公告)日：2021-01-19

申请号：US16374351

申请日：2019-04-03

Applicant: Winbond Electronics Corp.

Inventor： Hsu-Chi Cho ,  Cheng-Ta Yang

IPC: H01L27/11521 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/40 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11531 ,  H01L27/11558 ,  H01L27/11526 ,  H01L27/115 ,  H01L29/788

Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.

公开(公告)号：US20180342527A1

公开(公告)日：2018-11-29

申请号：US15871074

申请日：2018-01-15

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L27/11521 ,  H01L27/11529 ,  H01L27/11546

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/49

Abstract: A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

公开(公告)号：US11335568B2

公开(公告)日：2022-05-17

申请号：US16872760

申请日：2020-05-12

Applicant: Winbond Electronics Corp.

Inventor： Ting-Wei Wu ,  Cheng-Ta Yang ,  Hsin-Hung Chou

IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/033

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.

公开(公告)号：US11289612B2

公开(公告)日：2022-03-29

申请号：US16823800

申请日：2020-03-19

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L21/00 ,  H01L29/788 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11531 ,  H01L21/28

Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

公开(公告)号：US10438958B2

公开(公告)日：2019-10-08

申请号：US15871074

申请日：2018-01-15

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L27/11 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11529 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.