公开(公告)号：US12183833B2

公开(公告)日：2024-12-31

申请号：US17592832

申请日：2022-02-04

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B41/49

Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

公开(公告)号：US20180342527A1

公开(公告)日：2018-11-29

申请号：US15871074

申请日：2018-01-15

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L27/11521 ,  H01L27/11529 ,  H01L27/11546

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/49

Abstract: A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

公开(公告)号：US11289612B2

公开(公告)日：2022-03-29

申请号：US16823800

申请日：2020-03-19

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L21/00 ,  H01L29/788 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11531 ,  H01L21/28

Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

公开(公告)号：US10438958B2

公开(公告)日：2019-10-08

申请号：US15871074

申请日：2018-01-15

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L27/11 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11529 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

公开(公告)号：US10418440B2

公开(公告)日：2019-09-17

申请号：US15690298

申请日：2017-08-30

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L21/02 ,  H01L21/336 ,  H01L29/06 ,  H01L27/11517 ,  H01L21/762 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

公开(公告)号：US20190088486A1

公开(公告)日：2019-03-21

申请号：US16112780

申请日：2018-08-27

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L21/28 ,  H01L21/762 ,  H01L27/11521 ,  H01L21/02 ,  H01L29/423

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first conductive layer, a first oxide layer, and a hardmask layer are sequentially formed on a substrate. The hardmask layer and the first oxide layer are patterned to form a stacking structure including a hardmask pattern and a first oxide pattern. An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer, and a region of the first conductive layer adjacent to a sidewall of the stacking structure are oxidized to form an extending oxide pattern. The second oxide layer is removed. The stacking structure is applied as a mask to remove an exposed portion of the first conductive layer and the substrate therebelow, such that a first conductive structure and a recess in the substrate are formed. The stacking structure is removed. The extending oxide pattern is removed.

公开(公告)号：US20180350608A1

公开(公告)日：2018-12-06

申请号：US15867736

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L29/42324 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/02345 ,  H01L21/02359 ,  H01L21/31111 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/4916 ,  H01L29/518

Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

公开(公告)号：US10566337B2

公开(公告)日：2020-02-18

申请号：US16215666

申请日：2018-12-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L27/11531 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/11541 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/28

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

公开(公告)号：US20190341449A1

公开(公告)日：2019-11-07

申请号：US16516242

申请日：2019-07-18

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/11517 ,  H01L21/28 ,  H01L27/11521

Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.

公开(公告)号：US20180308929A1

公开(公告)日：2018-10-25

申请号：US15690298

申请日：2017-08-30

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L29/06 ,  H01L27/11517 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/7881

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.