公开(公告)号：US20230335510A1

公开(公告)日：2023-10-19

申请号：US17724063

申请日：2022-04-19

Applicant: XILINX, INC.

Inventor： Po-Wei CHIU ,  Tzu-No CHEN ,  Hong SHI ,  Li-Sheng WENG ,  Young Soo LEE

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.

公开(公告)号：US20240055359A1

公开(公告)日：2024-02-15

申请号：US17888293

申请日：2022-08-15

Applicant: XILINX, INC.

Inventor： Li-Sheng WENG ,  Suresh RAMALINGAM

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/498 ,  H01L21/50

CPC classification number: H01L23/5389 ,  H01L23/5384 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5385 ,  H01L28/40 ,  H01L28/10 ,  H01L23/49816 ,  H01L21/50 ,  H01L2224/16227 ,  H01L24/16

Abstract: A chip package and methods for fabricating the same are provided that include integrated devices embedded and coupled in series between a lower surface of a package substrate and an integrated circuit die of the chip package. In some examples, the integrated devices are disposed side by side embedded in a common package substrate. In other examples, one of the series coupled integrated devices is embedded in a first package substrate while another of the series coupled integrated devices is embedded in a second package substrate that is stacked directly in contact with the first package substrate. The integrated devices may be passive and/or active integrated devices.

公开(公告)号：US20230326842A1

公开(公告)日：2023-10-12

申请号：US17718220

申请日：2022-04-11

Applicant: XILINX, INC.

Inventor： Li-Sheng WENG ,  Chun-Yuan CHENG ,  Chao-Chin LEE

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L24/08

Abstract: A chip package and method for fabricating the same are provided that includes a power delivery network (PDN) with non-uniform electrical conductance. The electrical conductance through each current path of the PDN may be selected to balance the distribution of current flow across the current paths through the chip package, thus compensating for areas of high and low current draw found in conventional designs.

公开(公告)号：US20240071958A1

公开(公告)日：2024-02-29

申请号：US17896972

申请日：2022-08-26

Applicant: XILINX, INC.

Inventor： Hong SHI ,  Li-Sheng WENG ,  Frank Peter LAMBRECHT ,  Jing JING ,  Shuxian WU

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2924/1427 ,  H01L2924/30107

Abstract: A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.

公开(公告)号：US20240178087A1

公开(公告)日：2024-05-30

申请号：US18070380

申请日：2022-11-28

Applicant: XILINX, INC.

Inventor： Li-Sheng WENG ,  Alexander Helmut PFEIFFENBERGER

IPC: H01L23/31 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L25/162 ,  H01L25/50

Abstract: Chip packages are described herein that includes integrated passive devices embedded in a core of a substrate of the chip package, such as a package substrate or an interposer, that shield routings coupled to inductors from adjacent through-substrate conductive paths (e.g., vias). In one example, a chip package includes an integrated circuit (IC) die mounted to a substrate. A core of the substrate has a plurality of inductor routing vias, a plurality of signal transmission vias, and a plurality of ground and power routing vias. A first integrated passive device (IPD) is disposed in the core and separates at least one of the plurality of inductor routing vias from an adjacent via, the adjacent via being one of the plurality of signal transmission vias or one of the plurality of ground and power routing vias.

公开(公告)号：US20230253380A1

公开(公告)日：2023-08-10

申请号：US17669252

申请日：2022-02-10

Applicant: XILINX, INC.

Inventor： Li-Sheng WENG ,  Suresh RAMALINGAM ,  Hong SHI

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/24 ,  H01L2224/24265 ,  H01L2924/19103 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2224/244 ,  H01L2224/24226

Abstract: A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.