公开(公告)号：US11190178B1

公开(公告)日：2021-11-30

申请号：US17083191

申请日：2020-10-28

Applicant: XILINX, INC.

Inventor： Diarmuid Collins ,  Edward Cullen ,  Ionut C. Cical

IPC: H03K17/16 ,  H03K17/687 ,  H03K17/693 ,  G05F1/10 ,  G05F1/12 ,  H03K17/08 ,  H03K17/06

Abstract: Examples described herein provide an apparatus having a circuit with a grounding circuit and a switch. The apparatus generally includes a gate induced drain leakage (GIDL) protection circuit coupled to the switch and to an output voltage. The GIDL protection circuit may include a switch protection circuit configured to maintain a drain voltage of the switch less than a first supply voltage (Vdd) when the circuit is in an OFF state; and a ground protection circuit configured to maintain a drain voltage of the grounding circuit less than the first supply voltage when the circuit is in an ON state.

公开(公告)号：US10418994B1

公开(公告)日：2019-09-17

申请号：US15647756

申请日：2017-07-12

Applicant: Xilinx, Inc.

Inventor： Edward Cullen ,  Ionut C. Cical

IPC: H03K19/00 ,  H03K19/177

Abstract: A circuit for extending the bandwidth of a termination block is described. The circuit comprises an I/O contact configured to receive an input signal; and a termination circuit coupled to the I/O contact, wherein the termination circuit comprises a plurality of trim legs coupled between a power supply and the I/O contact, each trim leg having a switch to control the impedance in the trim leg.

公开(公告)号：US09054096B2

公开(公告)日：2015-06-09

申请号：US13626829

申请日：2012-09-25

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Edward Cullen ,  Donnacha Lowney

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract translation: 公开了一种装置的实施例。 对于该装置的该实施例，插入器具有第一通孔。 第一互连和第二互连分别耦合在插入器的相对表面上。 第一互连的第一部分和第一互连的第二部分彼此间隔开，在它们之间限定隔离区。 衬底具有第二通孔。 第三互连和第二互连分别耦合在封装衬底的相对表面上。 第一通孔的第一部分和第二通孔的第一部分都在隔离区域中并且彼此耦合，具有第二互连的第一部分。

公开(公告)号：US10120399B1

公开(公告)日：2018-11-06

申请号：US15848357

申请日：2017-12-20

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Edward Cullen ,  John K. Jennings

IPC: G05F1/46 ,  G06F1/20

Abstract: An example method of trimming a voltage reference in an integrated circuit (IC) includes at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage. The method further includes measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values. The method further includes at a second temperature, sequencing through a second plurality of trim codes for the reference circuit. The method further includes measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values. The method further includes selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

公开(公告)号：US20170346455A1

公开(公告)日：2017-11-30

申请号：US15167197

申请日：2016-05-27

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Diarmuid Collins ,  Edward Cullen ,  Ionut C. Cical

IPC: H03F3/45 ,  H03F1/56

CPC classification number: H03F3/45179 ,  H03F1/301 ,  H03F1/56 ,  H03F3/45183 ,  H03F2200/459 ,  H03F2203/45288

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

公开(公告)号：US08890730B2

公开(公告)日：2014-11-18

申请号：US13843909

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Donnacha Lowney ,  Christophe Erdmann ,  Edward Cullen

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/742

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract translation: 公开了一种用于校准信号转换器的装置。 该装置包括第一数模转换器（“DAC”）和耦合到第一DAC的输出端口的校准系统。 校准系统包括第二DAC。 校准系统被配置为响应于第一DAC的输出中的寄生光谱性能参数提供调整信号。 寄生光谱性能参数对与第一个DAC相关的定时误差敏感。 校准系统被耦合以向第一DAC提供调整信号以校正第一DAC的定时误差。

公开(公告)号：US11181426B1

公开(公告)日：2021-11-23

申请号：US16268124

申请日：2019-02-05

Applicant: Xilinx, Inc.

Inventor： Edward Cullen ,  Umanath R. Kamath ,  John K. Jennings ,  Diarmuid Collins ,  Ionut C. Cical

IPC: G01K7/00 ,  G01K15/00 ,  G01K7/01 ,  G01K1/00

Abstract: A temperature sensor includes a current source to produce a first bias current and a second bias current, a plurality of diodes, and temperature estimation circuitry. The plurality of diodes includes at least a first diode to receive the first bias current and a second diode to receive the second bias current. The temperature estimate circuitry measures a first voltage bias across the first diode resulting from the first bias current and a second voltage bias across the second diode resulting from the second bias current, and estimates a temperature of an environment of the temperature sensor based at least in part on the first voltage bias and the second voltage bias. The temperature sensor further includes error detection circuitry to measure at least one of the first or second bias currents and determine an amount of error in the temperature estimate based at least in part on the measurement.

公开(公告)号：US09935597B2

公开(公告)日：2018-04-03

申请号：US15167197

申请日：2016-05-27

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Diarmuid Collins ,  Edward Cullen ,  Ionut C. Cical

IPC: H03F3/45 ,  H03F1/56

CPC classification number: H03F3/45179 ,  H03F1/301 ,  H03F1/56 ,  H03F3/45183 ,  H03F2200/459 ,  H03F2203/45288

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

公开(公告)号：US09419636B1

公开(公告)日：2016-08-16

申请号：US14682868

申请日：2015-04-09

Applicant: Xilinx, Inc.

Inventor： April M. Graham ,  Edward Cullen ,  Conrado K. Mesadri

IPC: H03M1/66 ,  H03M1/00 ,  H03K3/012 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03M1/0836 ,  H03M1/747

Abstract: In one example, a current steering circuit includes an output transistor pair responsive to a first gate bias voltage. The current steering circuit further includes a first switch comprising a first source-coupled transistor pair coupled to the output transistor pair and responsive to a first differential gate voltage, and a second switch comprising a second source-coupled transistor pair coupled to the output transistor pair and responsive to a second differential gate voltage. The current steering circuit further includes a current source configured to source a bias current. The current steering circuit further includes a third switch comprising a third source-coupled transistor pair coupled between the current source and each of the first switch and the second switch, the third source-coupled transistor pair responsive to a third differential gate voltage.

Abstract translation: 在一个示例中，电流控制电路包括响应于第一栅极偏置电压的输出晶体管对。 电流转向电路还包括第一开关，其包括耦合到输出晶体管对并响应于第一差分栅极电压的第一源极耦合晶体管对，以及包括耦合到输出晶体管对的第二源极耦合晶体管对的第二开关 并响应于第二差分栅极电压。 电流转向电路还包括被配置为馈送偏置电流的电流源。 电流转向电路还包括第三开关，其包括耦合在电流源与第一开关和第二开关中的每一个之间的第三源极耦合晶体管对，第三源极耦合晶体管对响应第三差分栅极电压。

公开(公告)号：US20140132369A1

公开(公告)日：2014-05-15

申请号：US13675780

申请日：2012-11-13

Applicant: Xilinx, Inc.

Inventor： Donnacha Lowney ,  Edward Cullen

IPC: H01P1/20 ,  H04B3/20

CPC classification number: H01P1/20 ,  G11C27/024 ,  H03H7/0123 ,  H03H7/38 ,  H03H2007/013 ,  H04B3/20

Abstract: A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise.

Abstract translation: 电路包括第一输入端，第一传输线，通过第一传输线耦合到第一输入端的第一采样开关，耦合到采样开关的第一采样电容器和耦合到第一开路四分之一波长短截线 所述第一传输线，所述第一开路四分之一波长短截线被配置为减少所述第一传输线上的反冲噪声。 一种用于减少电路中的反冲噪声的方法包括确定与电路的第一传输线上的反冲噪声相关联的频率，该电路具有耦合到第一传输线的输入端，配置开路四分之一波长的长度 短截线对应于所确定的频率，并且将开路四分之一波长短截线耦合到第一传输线以滤除与反冲噪声相关联的频率。