公开(公告)号：US09584144B1

公开(公告)日：2017-02-28

申请号：US15135073

申请日：2016-04-21

Applicant: Xilinx, Inc.

Inventor： Lei Zhou ,  Hiva Hedayati

IPC: H03M1/38 ,  H03M1/00 ,  H03K5/15 ,  H03K19/00 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03K19/0013 ,  H03K5/15026 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462

Abstract: A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.

Abstract translation: 时钟发生器包括：接收全局时钟信号的第一输入; 用于接收完成信号的第二输入; 第三输入端，用于从比较器接收转换周期中的差分输出; 以及逻辑电路，被配置为至少部分地基于所述全局时钟信号和所述差分输出来产生控制时钟信号，并且将所述控制时钟信号提供给所述比较器用于下一个转换周期; 并且其中所述逻辑电路还被配置为响应于指示在转换阶段中所需的转换周期的完成的所述完成信号来禁用所述控制时钟信号。

公开(公告)号：US10536151B1

公开(公告)日：2020-01-14

申请号：US16024473

申请日：2018-06-29

Applicant: Xilinx, Inc.

Inventor： Lei Zhou ,  Jinyung Namkoong ,  Stanley Y. Chen ,  Parag Upadhyaya

IPC: H03L7/08 ,  G06F1/06 ,  H03K3/03

Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

公开(公告)号：US09490832B1

公开(公告)日：2016-11-08

申请号：US14942601

申请日：2015-11-16

Applicant: Xilinx, Inc.

Inventor： Lei Zhou ,  Hiva Hedayati

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/46

CPC classification number: H03M1/0872 ,  H03K3/35613 ,  H03M1/468

Abstract: An analog-to-digital converter circuit is described. The analog-to-digital converter circuit comprises an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a first amplifier current path and a second amplifier input associated with a second amplifier current path, and to generate an amplified differential analog input signal at a first amplifier output associated with the first amplifier current path and a second amplifier output associated with the second amplifier current path; a first capacitor coupled between the first amplifier input and the second amplifier output; a second capacitor coupled between the second amplifier input and the first amplifier output; and a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the amplified differential analog input signal, at a first latch output and a second latch output.

Abstract translation: 描述了一种模拟 - 数字转换器电路。 模数转换器电路包括放大器电路，其被配置为在与第一放大器电流路径相关联的第一放大器输入端和与第二放大器电流路径相关联的第二放大器输入端接收差分模拟输入信号，并且产生放大 与第一放大器电流路径相关联的第一放大器输出处的差分模拟输入信号和与第二放大器电流路径相关联的第二放大器输出; 耦合在第一放大器输入和第二放大器输出之间的第一电容器; 耦合在第二放大器输入和第一放大器输出之间的第二电容器; 以及锁存电路，其具有耦合到第一放大器输出的第一锁存器输入和耦合到第二放大器输出的第二锁存器输入，其中锁存电路被配置为基于放大的差分模拟输入信号产生差分数字输出信号， 在第一锁存器输出端和第二锁存器输出端。