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    Single-event upset mitigation in circuit design for programmable integrated circuits
    1.
    发明授权
    Single-event upset mitigation in circuit design for programmable integrated circuits 有权
    用于可编程集成电路的电路设计中的单事件缓解

    公开(公告)号：US09183338B1

    公开(公告)日：2015-11-10

    申请号：US14487286

    申请日：2014-09-16

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Pierre Maillard

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/505

    Abstract: In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.

    Abstract translation: 在一个示例中，实现可编程集成电路（IC）的电路设计的方法开始于识别电路设计的组合逻辑功能。 该方法根据第一约束将组合逻辑功能的第一阈值百分比映射到可编程IC的第一类型的查找表（LUT），有利于可编程IC的第二类型的LUT，第二类型的LUT 比第一类型的LUT更容易受到单事件的影响。 该方法基于映射生成可编程IC的电路设计的第一个物理实现。

    Power distribution for active-on-active die stack with reduced resistance
    3.
    发明授权
    Power distribution for active-on-active die stack with reduced resistance 有权

    公开(公告)号：US11041211B2

    公开(公告)日：2021-06-22

    申请号：US15902703

    申请日：2018-02-22

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain

    IPC: H01L23/522 ,  C12Q1/6886 ,  G01N33/574 ,  C07K16/32

    Abstract: Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.

    POWER DISTRIBUTION FOR ACTIVE-ON-ACTIVE DIE STACK WITH REDUCED RESISTANCE
    4.
    发明申请
    POWER DISTRIBUTION FOR ACTIVE-ON-ACTIVE DIE STACK WITH REDUCED RESISTANCE 审中-公开

    公开(公告)号：US20190259702A1

    公开(公告)日：2019-08-22

    申请号：US15902703

    申请日：2018-02-22

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain

    IPC: H01L23/522 ,  H01L25/00 ,  H01L23/48 ,  H01L25/065

    Abstract: Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.

    Circuit design-specific failure in time rate for single event upsets
    5.
    发明授权
    Circuit design-specific failure in time rate for single event upsets 有权
    电路设计特定的单事件故障时间速率故障

    公开(公告)号：US09483599B1

    公开(公告)日：2016-11-01

    申请号：US14494361

    申请日：2014-09-23

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  James Karp

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5022 ,  G06F17/5054 ,  G06F17/5081

    Abstract: Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.

    Abstract translation: 确定电路设计特定的集成电路（IC）的单事件故障的时间速率失败包括使用处理器确定用于目标IC的电路设计的多个关键互连多路复用器位，并确定关键的数量 查找表位用于电路设计。 使用处理器，使用关键互连复用器位数和关键查找表位数来估计目标IC的电路设计的设备漏洞因素。 可以存储估计的设备脆弱性因子，例如用于随后与其他电路设计的比较。

    Integrated circuits designed for multiple sets of criteria
    6.
    发明授权
    Integrated circuits designed for multiple sets of criteria 有权

    公开(公告)号：US10908598B1

    公开(公告)日：2021-02-02

    申请号：US16426945

    申请日：2019-05-30

    Applicant: XILINX, INC.

    Inventor： Praful Jain

    IPC: G05B19/418 ,  G06F30/30

    Abstract: Examples described herein provide a method for designing an integrated circuit (IC) for meeting different sets of criteria. In an example, different sets of criteria are identified for an IC design. The IC design is designed to meet the different sets of criteria based on expected manufacturing variation. The IC design is caused to be manufactured as IC products. At least some of the IC products are caused to be tested. The IC products are characterized as meeting respective ones of the different sets of criteria based on testing the at least some of the IC products.

    Forming and/or configuring stacked dies
    10.
    发明授权
    Forming and/or configuring stacked dies 有权

    公开(公告)号：US11961823B1

    公开(公告)日：2024-04-16

    申请号：US17354927

    申请日：2021-06-22

    Applicant: XILINX, INC.

    Inventor： Praful Jain ,  Martin Voogel ,  Brian Gaide

    IPC: H01L25/065 ,  H01L23/00

    CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/15311

    Abstract: Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two or more of the dies that are interchangeable are based on the characteristics.

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