公开(公告)号：US10977401B1

公开(公告)日：2021-04-13

申请号：US16724553

申请日：2019-12-23

Applicant: Xilinx, Inc.

Inventor： Jeffrey M. Arnold ,  Stephen L. Bade ,  Srinivas Beeravolu ,  Chukwuweta Chukwudebe ,  Anindita Patra ,  Nabeel Shirazi

IPC: G06F30/327 ,  G06F30/343 ,  G06F30/398

Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.

公开(公告)号：US11886789B1

公开(公告)日：2024-01-30

申请号：US17369192

申请日：2021-07-07

Applicant: Xilinx, Inc.

Inventor： Ayush Khemka ,  Srinivas Beeravolu ,  Kalyani Tummala ,  Jaipal Reddy Nareddy ,  Adithya Balaji Boda ,  Suman Kumar Timmireddy

IPC: G06F30/392 ,  G06F30/398 ,  G06F111/20

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/20

Abstract: Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.

公开(公告)号：US10891414B2

公开(公告)日：2021-01-12

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F30/34

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US20200372123A1

公开(公告)日：2020-11-26

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F17/50

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US08769449B1

公开(公告)日：2014-07-01

申请号：US13763317

申请日：2013-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Biping Wu ,  Kyle Corbett ,  Nabeel Shirazi ,  Shay P. Seng ,  Amit Kasat ,  Srinivas Beeravolu ,  Khang K. Dao ,  Jeffrey H. Seltzer ,  Christopher J. Case

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/66

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

Abstract translation: 公开了用于产生电路设计的方法。 响应于用户输入，在电路设计中实例化多个单元。 每个单元的接口参数的集合被布置成如由与该单元相对应的接口模型所指示的接口层级。 对于每个接口级别，包括在接口级别中的单元的接口参数的集合的值分别传播到直接连接到该单元的其他单元。 响应于将接口参数的值从多个小区的另一小区传播到小区，并且具有与传播值不同的对应接口参数的小区的小区响应于小区的对应接口参数的值 使用与对应的接口电平相关联的相应传播函数来确定。