公开(公告)号：US4530050A

公开(公告)日：1985-07-16

申请号：US408924

申请日：1982-08-17

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/36

CPC分类号： G06F9/30167 ,  G06F9/30152 ,  G06F9/3016

摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

摘要翻译： 一种用于执行可变长度指令的中央处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的种类和操作数的操作码无关。 每个操作数说明符由一个或多个数据字节形成，并且具有指示特定操作数说明符是否是最后一个操作数说明符的停止位标志。 通过添加停止位标志，可以共享操作数说明符，可以使用相同的操作码执行不同的处理。 在操作码解码装置提供指示最后一个操作数的输出的情况下，在对应的操作数说明符中没有检测到停止位平面，相应的指令被检测为错误。

公开(公告)号：US4783731A

公开(公告)日：1988-11-08

申请号：US030266

申请日：1987-03-24

申请人： Yoshihiro Miyazaki ,  Jushi Ide ,  Takeshi Kato ,  Hiroaki Nakanishi ,  Tadaaki Bandoh

发明人： Yoshihiro Miyazaki ,  Jushi Ide ,  Takeshi Kato ,  Hiroaki Nakanishi ,  Tadaaki Bandoh

IPC分类号： G06F12/16 ,  G06F9/46 ,  G06F11/36 ,  G06F12/14 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F11/3648 ,  G06F9/468

摘要： A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.

摘要翻译： 具有双公共存储器的多计算机系统，其中在公共存储器内设置指定的地址区域。 无论CPU处于在线模式还是调试模式，指定的地址区都可以访问，而只有当公用存储器的功能模式与访问模式一致时，除指定地址区域之外的任何区域才可访问 中央处理器。 对应于每个CPU，由CPU使用的地址被划分为多组地址，并且为各个地址组设置访问模式。

公开(公告)号：US4839846A

公开(公告)日：1989-06-13

申请号：US838941

申请日：1986-03-12

申请人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

发明人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/485 ,  G06F7/50 ,  G06F7/508 ,  G06F7/76

CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49957

摘要： An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

摘要翻译： 能够在浮点运算中高速进行圆形处理的运算部。 提供一种用于在一个代表全局的输出中表示全部1的信号和表示四舍五入的信号，进位查找电路和用于产生圆形精度信号的电路的条件下检测溢出的电路。 当溢出发生时，尾数产生为“1”。 操作单元兼容电气和电子工程师协会（IEEE）推荐的单，双和扩展精度。

公开(公告)号：US4811269A

公开(公告)日：1989-03-07

申请号：US916695

申请日：1986-10-08

申请人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

发明人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

IPC分类号： G06F7/487 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53

CPC分类号： G06F7/5324 ,  G06F2207/3896

摘要： A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.

摘要翻译： 一个用于切片乘法器的位片倍增电路，为分片乘法器产生乘积，并对乘积求和，得到乘法结果。 该电路包括一个限幅单元，用于对被乘数进行分片，对应的乘法单元数目与分片被乘数的数目相对应，并且与乘法单元对应地设置的加法单位，并对相应的乘法单元进行相乘结果的求和， 通过乘法单元在分片乘法器和被乘数的乘法运算中被乘数，乘法结果是通过将由加法单元产生的所有求和结果求和来获得的。

公开(公告)号：US4896258A

公开(公告)日：1990-01-23

申请号：US881407

申请日：1986-07-02

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hiroaki Nakanishi ,  Kenzi Hirose ,  Takao Kobayashi ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hiroaki Nakanishi ,  Kenzi Hirose ,  Takao Kobayashi ,  Yoshihiro Miyazaki

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/44

CPC分类号： G06F9/30181 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/3557 ,  G06F9/4438

摘要： A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

公开(公告)号：US4486834A

公开(公告)日：1984-12-04

申请号：US485020

申请日：1983-04-14

申请人： Yoshiki Kobayashi ,  Hideo Maejima ,  Tadaaki Bandoh ,  Hiroaki Nakanishi

发明人： Yoshiki Kobayashi ,  Hideo Maejima ,  Tadaaki Bandoh ,  Hiroaki Nakanishi

IPC分类号： G06F12/16 ,  G06F11/16 ,  G06F11/20 ,  G06F11/26 ,  G06F15/167 ,  G11C29/00 ,  G06F13/00 ,  G11C9/00

CPC分类号： G06F11/2082 ,  G06F11/26 ,  G06F15/167 ,  G11C29/74 ,  G06F11/2064

摘要： A multi-computer system having a dual common memory adapted to perform Read/Write operations by means of a plurality of computers. Each computer in the system consists of a central processing unit, a main memory and a dual memory access unit. The dual memory access unit is adapted to provide a status signal representative of whether the data from the common memory is correct or not and a maintenance signal representative of whether a maintenance operation is demanded. A memory access is made only to the common memory demanding the maintenance when the program run by the computer is a maintenance program, and only to the normal common memory during the usual operation.

摘要翻译： 一种具有适于通过多个计算机执行读/写操作的双公共存储器的多计算机系统。 系统中的每台计算机都由中央处理单元，主存储器和双存储器存取单元组成。 双存储器访问单元适于提供表示来自公共存储器的数据是否正确的状态信号，以及表示是否需要维护操作的维护信号。 只有当计算机运行的程序是维护程序时才需要进行维护的公共存储器的存储器访问，并且在正常操作期间仅对正常的公共存储器进行存储器访问。

公开(公告)号：US08491776B2

公开(公告)日：2013-07-23

申请号：US12674001

申请日：2007-08-31

申请人： Hiroaki Nakanishi ,  Satoshi Konishi ,  Keisuke Naka

发明人： Hiroaki Nakanishi ,  Satoshi Konishi ,  Keisuke Naka

IPC分类号： G01N30/00 ,  G01N30/26 ,  G01N30/88

CPC分类号： G21G4/00 ,  B01D59/42 ,  G21G1/001 ,  G21G2001/0015 ,  Y10T156/10

摘要： A flowcell 2 is constituted of insulating substrates 2a and 2b. The two substrates 2a and 2b have been directly bonded to each other by a bonding method for attaining tenacious bonding, for example, anodic bonding or hydrofluoric acid bonding. A channel 6 has been formed at the interface between the substrates 2a and 2b. Part of the substrate 2a which faces the channel 6 has a carbon electrode 4a formed thereon by sintering a pasty carbon material, the electrode 4a extending along the channel 6. On the other hand, the substrate 2b has a groove 6a serving as the channel 6, and has an electrode 4b made of a metal film formed on a bottom surface of the groove 6a.

摘要翻译： 流通池2由绝缘基板2a和2b构成。 两个基板2a和2b已经通过用于实现顽固结合的接合方法彼此直接接合，例如阳极接合或氢氟酸粘合。 在基板2a和2b之间的界面处形成通道6。 面向通道6的基板2a的一部分通过烧结糊状碳材料而形成在其上的碳电极4a，电极4a沿通道6延伸。另一方面，基板2b具有用作通道6的槽6a 并且具有由形成在凹槽6a的底表面上的金属膜制成的电极4b。

公开(公告)号：US06759644B2

公开(公告)日：2004-07-06

申请号：US10100225

申请日：2002-03-14

申请人： Susumu Mizuhara ,  Arata Nakamura ,  Hiroaki Nakanishi

发明人： Susumu Mizuhara ,  Arata Nakamura ,  Hiroaki Nakanishi

IPC分类号： H01J4014

CPC分类号： G01J1/44 ,  G01S7/493 ,  G01S7/527

摘要： A sensor has an emitting device for emitting radiation pulses repeatedly and a receiving device for receiving these pulses. The receiving device includes a converter such as a photoelectric converter to convert the received radiation pulses into electrical pulses. On the basis of a known waveform characteristic or characteristics of true electrical pulse it is judged if a pulse which appears on the output line of the converter is a true electrical pulse caused by receiving the radiation pulse emitted from the emitting device or a false electrical pulse caused by noise. The result of this judgment is outputted from an output device. The emitting device may serve to emit the pulses according to a specified bit pattern and the receiving device may serve to compare the pattern of received pulses with a standard bit pattern and to thereby distinguish between true and false electrical pulses.

摘要翻译： 传感器具有用于重复发射辐射脉冲的发射装置和用于接收这些脉冲的接收装置。 接收装置包括诸如光电转换器的转换器，以将接收到的辐射脉冲转换成电脉冲。 基于已知的波形特性或真电脉冲的特性，判断出现在转换器的输出线上的脉冲是否是由接收从发射装置发射的辐射脉冲或假电脉冲引起的真电脉冲 造成噪音 该判断结果从输出装置输出。 发射装置可以用于根据指定的位模式发射脉冲，并且接收装置可以用于将接收的脉冲的模式与标准位模式进行比较，从而区分真假电脉冲。

公开(公告)号：US06717129B1

公开(公告)日：2004-04-06

申请号：US10617570

申请日：2003-07-11

申请人： Susumu Mizuhara ,  Arata Nakamura ,  Hiroaki Nakanishi

发明人： Susumu Mizuhara ,  Arata Nakamura ,  Hiroaki Nakanishi

IPC分类号： H01J4014

CPC分类号： G01S17/026 ,  G01S7/487 ,  H03K17/941

摘要： A photoelectric sensor has an emitting device for emitting radiation pulses repeatedly and a receiving device for receiving these pulses. The receiving device includes a converter such as a photoelectric converter to convert the received radiation pulses into electrical pulses. On the basis of a known waveform characteristic or characteristics of true electrical pulse it is judged if a pulse which appears on the output line of the converter is a true electrical pulse caused by receiving the radiation pulse emitted from the emitting device or a false electrical pulse caused by noise. The result of this judgment is outputted from an output device. The emitting device may serve to emit the pulses according to a specified bit pattern and the receiving device may serve to compare the pattern of received pulses simultaneously with two or more standard bit patterns and to thereby distinguish between true and false electrical pulses.

摘要翻译： 光电传感器具有重复发射辐射脉冲的发射装置和用于接收这些脉冲的接收装置。 接收装置包括诸如光电转换器的转换器，以将接收到的辐射脉冲转换成电脉冲。 基于已知的波形特性或真电脉冲的特性，判断出现在转换器的输出线上的脉冲是否是由接收从发射装置发射的辐射脉冲或假电脉冲引起的真电脉冲 造成噪音 该判断结果从输出装置输出。 发射装置可以用于根据指定的位模式发射脉冲，并且接收装置可以用于将接收到的脉冲的模式与两个或更多个标准位模式同时比较，从而区分真实和错误的电脉冲。

公开(公告)号：US06075267A

公开(公告)日：2000-06-13

申请号：US806447

申请日：1997-02-26

申请人： Satoru Taji ,  Hiroaki Nakanishi

发明人： Satoru Taji ,  Hiroaki Nakanishi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A non-volatile semiconductor memory device includes a substrate and a continuously formed drain diffusion layer and a continuously formed source diffusion layer which are alternately arranged within the substrate. Floating gates are disposed via a tunnel insulating film on the substrate so that they are adjacent to the drain diffusion layer. The floating gates are opposed to each other with the drain diffusion layer therebetween, and spaced away from the source diffusion layer. A control gate extends in a direction orthogonal with a direction in which the source and drain diffusion layers extend, the control gate being formed on the floating gates and the substrate via an insulating film. A select channel is provided between the floating gate closest to the source diffusion layer and the source diffusion layer. A thick insulating film is provided between the drain diffusion layer and the control gate between the floating gates which are opposed to each other with the drain diffusion layer therebetween.

摘要翻译： 非易失性半导体存储器件包括基板和连续形成的漏极扩散层和连续形成的源极扩散层，其交替地布置在基板内。 浮动栅极通过衬底上的隧道绝缘膜设置，使得它们与漏极扩散层相邻。 浮置栅极彼此相对，其间具有漏极扩散层，并且与源极扩散层间隔开。 控制栅极在与源极和漏极扩散层延伸的方向正交的方向上延伸，控制栅极通过绝缘膜形成在浮动栅极和衬底上。 在最靠近源极扩散层的浮置栅极和源极扩散层之间提供选择沟道。 在漏极扩散层和控制栅极之间的漏极扩散层之间彼此相对的浮置栅极之间设置厚的绝缘膜。