公开(公告)号：US4896258A

公开(公告)日：1990-01-23

申请号：US881407

申请日：1986-07-02

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hiroaki Nakanishi ,  Kenzi Hirose ,  Takao Kobayashi ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hiroaki Nakanishi ,  Kenzi Hirose ,  Takao Kobayashi ,  Yoshihiro Miyazaki

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/44

CPC分类号： G06F9/30181 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/3557 ,  G06F9/4438

摘要： A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

公开(公告)号：US5146569A

公开(公告)日：1992-09-08

申请号：US674398

申请日：1991-03-25

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Morioka Takayuki ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Morioka Takayuki ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC分类号： G06F11/14

CPC分类号： G06F11/141

摘要： Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

摘要翻译： 微程序控制数据处理装置中的指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

公开(公告)号：US4839846A

公开(公告)日：1989-06-13

申请号：US838941

申请日：1986-03-12

申请人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

发明人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/485 ,  G06F7/50 ,  G06F7/508 ,  G06F7/76

CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49957

摘要： An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

摘要翻译： 能够在浮点运算中高速进行圆形处理的运算部。 提供一种用于在一个代表全局的输出中表示全部1的信号和表示四舍五入的信号，进位查找电路和用于产生圆形精度信号的电路的条件下检测溢出的电路。 当溢出发生时，尾数产生为“1”。 操作单元兼容电气和电子工程师协会（IEEE）推荐的单，双和扩展精度。

公开(公告)号：US4811269A

公开(公告)日：1989-03-07

申请号：US916695

申请日：1986-10-08

申请人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

发明人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

IPC分类号： G06F7/487 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53

CPC分类号： G06F7/5324 ,  G06F2207/3896

摘要： A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.

摘要翻译： 一个用于切片乘法器的位片倍增电路，为分片乘法器产生乘积，并对乘积求和，得到乘法结果。 该电路包括一个限幅单元，用于对被乘数进行分片，对应的乘法单元数目与分片被乘数的数目相对应，并且与乘法单元对应地设置的加法单位，并对相应的乘法单元进行相乘结果的求和， 通过乘法单元在分片乘法器和被乘数的乘法运算中被乘数，乘法结果是通过将由加法单元产生的所有求和结果求和来获得的。

公开(公告)号：US5003458A

公开(公告)日：1991-03-26

申请号：US111618

申请日：1987-10-23

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC分类号： G06F11/14

CPC分类号： G06F11/141

摘要： Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

摘要翻译： 在微程序控制数据处理装置中进行指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

公开(公告)号：US4530050A

公开(公告)日：1985-07-16

申请号：US408924

申请日：1982-08-17

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/36

CPC分类号： G06F9/30167 ,  G06F9/30152 ,  G06F9/3016

摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

摘要翻译： 一种用于执行可变长度指令的中央处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的种类和操作数的操作码无关。 每个操作数说明符由一个或多个数据字节形成，并且具有指示特定操作数说明符是否是最后一个操作数说明符的停止位标志。 通过添加停止位标志，可以共享操作数说明符，可以使用相同的操作码执行不同的处理。 在操作码解码装置提供指示最后一个操作数的输出的情况下，在对应的操作数说明符中没有检测到停止位平面，相应的指令被检测为错误。

公开(公告)号：US4807113A

公开(公告)日：1989-02-21

申请号：US930532

申请日：1986-11-14

申请人： Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Ryosei Hiraoka ,  Takayuki Morioka ,  Yoshihiro Miyazaki

发明人： Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Ryosei Hiraoka ,  Takayuki Morioka ,  Yoshihiro Miyazaki

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/42 ,  G06F9/34 ,  G06F9/36

CPC分类号： G06F9/3016 ,  G06F9/3824

摘要： A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address of a microprogram from a decoding unit, a ready status signal and a signal from the decoding unit indicating whether a destination of an operand is in a general purpose register or in a memory unit, and writes an operand into a destination address of a register on the memory unit under control of a microprogram. Because the destination of the operand is indicated by the instruction decoding unit, it is not necessary to determine this information by microinstruction execution, with the result that execution of the instruction can be performed at high speed.

摘要翻译： 微程序控制数据处理装置执行多操作指令，其中提供一个或多个操作数说明符，用于独立于指令的操作码指定每个操作数的寻址。 指令执行单元从解码单元接收微程序的顶部地址，就绪状态信号和来自解码单元的指示操作数的目的地是否在通用寄存器中或存储单元中的信号，并且将操作数 在微程序的控制下，转换到存储器单元上的寄存器的目的地地址。 由于操作数的目的地由指令解码单元指示，所以不需要通过微指令执行来确定该信息，结果可以高速执行指令。

公开(公告)号：US4783731A

公开(公告)日：1988-11-08

申请号：US030266

申请日：1987-03-24

申请人： Yoshihiro Miyazaki ,  Jushi Ide ,  Takeshi Kato ,  Hiroaki Nakanishi ,  Tadaaki Bandoh

发明人： Yoshihiro Miyazaki ,  Jushi Ide ,  Takeshi Kato ,  Hiroaki Nakanishi ,  Tadaaki Bandoh

IPC分类号： G06F12/16 ,  G06F9/46 ,  G06F11/36 ,  G06F12/14 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F11/3648 ,  G06F9/468

摘要： A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.

摘要翻译： 具有双公共存储器的多计算机系统，其中在公共存储器内设置指定的地址区域。 无论CPU处于在线模式还是调试模式，指定的地址区都可以访问，而只有当公用存储器的功能模式与访问模式一致时，除指定地址区域之外的任何区域才可访问 中央处理器。 对应于每个CPU，由CPU使用的地址被划分为多组地址，并且为各个地址组设置访问模式。

公开(公告)号：US4644490A

公开(公告)日：1987-02-17

申请号：US599167

申请日：1984-04-11

申请人： Takao Kobayashi ,  Shigeo Abe ,  Tadaaki Bandoh ,  Masao Takatoo ,  Hidekazu Matsumoto ,  Hideyuki Hara

发明人： Takao Kobayashi ,  Shigeo Abe ,  Tadaaki Bandoh ,  Masao Takatoo ,  Hidekazu Matsumoto ,  Hideyuki Hara

IPC分类号： G06F7/485 ,  G06F5/01 ,  G06F7/00 ,  G06F7/50 ,  G06F7/508 ,  G06F7/76

CPC分类号： G06F7/485 ,  G06F2207/3884

摘要： A pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal to produce a floating point sum or difference data in a sign-magnitude format. In a first stage of the adder, the magnitudes of the exponent data of the input data are compared by a subtractor or a comparator and the magnitudes of the mantissa data of the input data are compared by a subtractor or a comparator. An actual operation mode for the mantissa data of the input data is determined, on the basis of the compare results of the exponent data and the mantissa data and the external operation mode designation signals, so that the operation result data is always expressed in a sign-magnitude format.

摘要翻译： 一种流水线加法器，用于根据外部操作模式指定信号，加上或减去由符号数据，指数数据和符号幅度格式表示的尾数表示的两个浮点输入数据，以产生浮点和或差 数据格式的数据。 在加法器的第一级中，通过减法器或比较器比较输入数据的指数数据的大小，并通过减法器或比较器比较输入数据的尾数数据的大小。 基于指数数据和尾数数据和外部操作模式指定信号的比较结果确定输入数据的尾数数据的实际操作模式，使得操作结果数据总是以符号表示 -magnitude格式。

公开(公告)号：US4523272A

公开(公告)日：1985-06-11

申请号：US366785

申请日：1982-04-08

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Ryosei Hiraoka ,  Hidekazu Matsumoto ,  Jushi Ide ,  Tetsuya Kawakami

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Ryosei Hiraoka ,  Hidekazu Matsumoto ,  Jushi Ide ,  Tetsuya Kawakami

IPC分类号： G06F13/374 ,  G06F15/16 ,  G06F15/40

CPC分类号： G06F13/374

摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

摘要翻译： 在具有主存储器和通过公共地址总线连接的多个处理器，数据总线和用于数据传送的应答总线的多处理器系统中，为每个主存储器和处理器提供数据传输装置，并且包括总线请求控制线， 传送总线请求信号和总线控制信号;以及总线控制器，用于响应于总线请求控制线上的信号和请求信号单独控制地址总线，数据总线和应答总线的选择。 可以在一个周期内重叠处理，如数据写入和数据写入应答或数据读取和数据读取应答。