公开(公告)号：US08916975B2

公开(公告)日：2014-12-23

申请号：US12493617

申请日：2009-06-29

申请人： Chang Kun Park ,  Seong Hwi Song ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang

发明人： Chang Kun Park ,  Seong Hwi Song ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L23/5286 ,  H01L24/09 ,  H01L27/1052 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/091 ,  H01L2224/09515 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/30101 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

摘要翻译： 半导体存储器件包括具有芯片焊盘形成区域的半导体电路基板。 在芯片焊盘区域一侧的半导体电路基板上形成一对数据线。 一对数据线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸。 这对数据线被布置为彼此相邻并且接收一对差分数据信号。 电源线形成在芯片焊盘区域的另一侧的半导体电路基板上。 电源线沿着半导体电路基板的芯片焊盘区域延伸的方向延伸，并且电源线接收电力。

公开(公告)号：US08810274B2

公开(公告)日：2014-08-19

申请号：US13657123

申请日：2012-10-22

申请人： Yong Ju Kim ,  Hyung Soo Kim ,  Hae Rang Choi ,  Jae Min Jang

发明人： Yong Ju Kim ,  Hyung Soo Kim ,  Hae Rang Choi ,  Jae Min Jang

IPC分类号： H03K17/16

CPC分类号： H04L25/0298

摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

摘要翻译： 片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

公开(公告)号：US07915939B2

公开(公告)日：2011-03-29

申请号：US12407727

申请日：2009-03-19

申请人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

发明人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

IPC分类号： H03K5/04

CPC分类号： H03K5/1565 ,  H03K2005/00052 ,  H03L7/0814

摘要： A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.

摘要翻译： 占空比校正装置包括：固定延迟单元，被配置为将固定延迟时间设置为DLL时钟信号，并产生延迟上升时钟信号; 可变延迟单元，被配置为响应于控制信号延迟所述DLL时钟信号并产生延迟下降时钟信号; 占空比校正单元，被配置为产生与延迟上升时钟信号和延迟下降时钟信号的边沿定时一致的校正上升时钟信号和校正下降时钟信号; 以及延迟控制单元，被配置为检测所述校正上升时钟信号和所述校正下降时钟信号的占空比，并产生所述控制信号。

公开(公告)号：US20100060332A1

公开(公告)日：2010-03-11

申请号：US12340912

申请日：2008-12-22

申请人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

发明人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

IPC分类号： H03L7/06

CPC分类号： H03K3/0322 ,  H03K5/1504 ,  H03K2005/00208 ,  H03L7/083 ,  H03L7/24

摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.

摘要翻译： 半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号 电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

公开(公告)号：US20090206901A1

公开(公告)日：2009-08-20

申请号：US12333193

申请日：2008-12-11

申请人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Jae Min Jang ,  Hyung Soo Kim ,  Ji Wang Lee ,  Chang Kun Park ,  Ic Su Oh ,  Hae Rang Choi ,  Tae Jin Hwang

发明人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Jae Min Jang ,  Hyung Soo Kim ,  Ji Wang Lee ,  Chang Kun Park ,  Ic Su Oh ,  Hae Rang Choi ,  Tae Jin Hwang

IPC分类号： H03K5/04

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

摘要翻译： 一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到 所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平 输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

公开(公告)号：US20100309732A1

公开(公告)日：2010-12-09

申请号：US12647174

申请日：2009-12-24

申请人： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

发明人： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C7/1078 ,  G11C7/1087

摘要： A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.

摘要翻译： 用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。 第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。 第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。 第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。 第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。

公开(公告)号：US07800416B2

公开(公告)日：2010-09-21

申请号：US12340882

申请日：2008-12-22

申请人： Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

发明人： Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

IPC分类号： H03K3/00

CPC分类号： G11C7/1051 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C11/4093

摘要： A data output circuit includes a pre-driving block configured to receive input data, generate a plurality of pull-up signals and pull-down signals, and change enable times of the pull-up signals and the pull-down signals in response to a plurality of control signals, and a main driving block configured to generate output data in response to the pull-up signals and the pull-down signals.

摘要翻译： 数据输出电路包括：预驱动块，被配置为接收输入数据，产生多个上拉信号和下拉信号，以及响应于一个上拉信号和下拉信号改变使能时间 多个控制信号和主驱动块，被配置为响应于上拉信号和下拉信号而产生输出数据。

公开(公告)号：US20100064163A1

公开(公告)日：2010-03-11

申请号：US12346675

申请日：2008-12-30

申请人： Hae Rang Choi ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

发明人： Hae Rang Choi ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

IPC分类号： G06F1/12

CPC分类号： G11C7/1051 ,  G06F1/12 ,  G11C7/1072 ,  G11C7/222

摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

摘要翻译： 半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及 数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

公开(公告)号：US20100034043A1

公开(公告)日：2010-02-11

申请号：US12333194

申请日：2008-12-11

申请人： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee- Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

发明人： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee- Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C5/14 ,  Y10T307/352 ,  Y10T307/391 ,  Y10T307/50 ,  Y10T307/505 ,  Y10T307/549 ,  Y10T307/555 ,  Y10T307/56 ,  Y10T307/565 ,  Y10T307/571 ,  Y10T307/576 ,  Y10T307/582 ,  Y10T307/587 ,  Y10T307/593

摘要： A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.

摘要翻译： 能够进行功率共享的半导体IC器件包括被配置为被提供第一电力的第一电力线，被配置为被提供第二电力的第二电力线，被配置为将第一电力线与第二电力连接的开关块 响应于第一控制信号的线路;以及功率共享控制块，被配置为根据多个操作命令信号产生控制信号。

公开(公告)号：US20090257301A1

公开(公告)日：2009-10-15

申请号：US12336423

申请日：2008-12-16

申请人： Ic Su Oh ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

发明人： Ic Su Oh ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.

摘要翻译： 半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压 电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平 以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及 电压产生单元，被配置为根据检测信号的电位来驱动外部电压 并输出外部电压作为输出电压。