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公开(公告)号：US6114890A
公开(公告)日：2000-09-05
申请号：US967658
申请日：1997-11-10
CPC分类号： H03L7/0805 , H03L7/0814 , H03L7/087
摘要： A circuit includes a first phase-adjustment circuit adjusting phases of rising edges and falling edges of an original signal, and a phase-delay circuit receiving a phase-adjusted signal from said first phase-adjustment circuit and generating a delay signal by delaying said phase-adjusted signal by a predetermined phase amount. The circuit further includes a phase-comparison circuit comparing phases of edges between said phase-adjusted signal and said delay signal so as to control said first phase-adjustment circuit such that said phases of edges satisfy a predetermined phase relation.
摘要翻译： 电路包括调整原始信号的上升沿和下降沿的相位的第一相位调整电路，以及从所述第一相位调整电路接收相位调整信号的相位延迟电路，并通过延迟所述相位产生延迟信号 - 调整信号预定相位量。 电路还包括相位比较电路，比较所述相位调整信号和所述延迟信号之间的边沿的相位，以便控制所述第一相位调整电路，使得所述边缘相位满足预定的相位关系。
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公开(公告)号：US5838604A
公开(公告)日：1998-11-17
申请号：US803448
申请日：1997-02-20
IPC分类号： G11C11/41 , G11C5/02 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C5/025 , G11C11/409 , G11C7/10
摘要： A semiconductor memory device includes a plurality of bit lines, first sense amplifiers each connected to a corresponding one of the plurality of bit lines, and a first data bus laid out in parallel to the plurality of bit lines and connected to the plurality of bit lines via gates and the first sense amplifiers. The semiconductor memory device further includes column-selection lines laid out perpendicularly to the plurality of bit lines to open at least one of the gates to connect the first data bus to the plurality of bit lines.
摘要翻译： 半导体存储器件包括多个位线，每个连接到多个位线中的相应一个位线的第一读出放大器和与多个位线并联布置并连接到多个位线的第一数据总线 通过门和第一感测放大器。 半导体存储器件还包括垂直于多个位线布置的列选择线，以打开至少一个栅极，以将第一数据总线连接到多个位线。
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公开(公告)号：US06343030B1
公开(公告)日：2002-01-29
申请号：US08754758
申请日：1996-11-21
IPC分类号： G11C1300
CPC分类号： G11C5/06 , G11C5/04 , H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device connected to at least one semiconductor device of the same type. The semiconductor device includes first pins, provided on a first side of the semiconductor device, for receiving signals commonly used with the at least one semiconductor device, and second pins, provided on a second side of the semiconductor device substantially perpendicular to the first side, for being connected to signal lines which are not connected to the at least one semiconductor device.
摘要翻译： 连接到相同类型的至少一个半导体器件的半导体器件。 半导体器件包括设置在半导体器件的第一侧上的第一引脚，用于接收与该至少一个半导体器件通用的信号，以及设置在该半导体器件的基本垂直于该第一侧的第二侧上的第二引脚， 用于连接到未连接到至少一个半导体器件的信号线。
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4.发明授权Signal-transfer system and semiconductor device for high-speed data transfer 失效用于高速数据传输的信号传输系统和半导体器件
公开(公告)号：US6097208A
公开(公告)日：2000-08-01
申请号：US823014
申请日：1997-03-21
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , G11C11/401 , H03K19/0175 , H03K19/018 , H03K17/16
CPC分类号： G06F13/4077
摘要： A signal-transfer system for transferring a signal via a line having no anti-signal-reflection resistor. The signal-transfer system includes a line having an equalized characteristic impedance Z.sub.0, and an output circuit having an output turn-on resistance Z.sub.0 /2 and outputting to the line a signal which has a voltage difference between a high level and a low level smaller than about 1 V.
摘要翻译： 一种用于通过没有抗信号反射电阻的线路传送信号的信号传输系统。 信号传输系统包括具有均衡特性阻抗Z0的线路和具有输出导通电阻Z0 / 2的输出电路，并且向线路输出具有较高电平和低电平之间的电压差的信号 比约1 V.
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公开(公告)号：US07941730B2
公开(公告)日：2011-05-10
申请号：US11443031
申请日：2006-05-31
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译： 半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。 用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。 通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。 因此，可以使用一种半导体存储器作为多种半导体存储器。 这消除了开发多种半导体存储器的需要，降低了开发成本。
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公开(公告)号：US07533196B2
公开(公告)日：2009-05-12
申请号：US11589840
申请日：2006-10-31
IPC分类号： G06F13/28
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译： 半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。 半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。 半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。
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7.发明授权公开(公告)号：US07428182B1
公开(公告)日：2008-09-23
申请号：US09372166
申请日：1999-08-11
申请人： Yoshinori Okajima
发明人： Yoshinori Okajima
IPC分类号： G11C8/00
CPC分类号： H04L12/42
摘要： An electronic circuit system has at least three macro circuits and a plurality of signal lines for connecting the macro circuits to one another into a loop. Each of the macro circuits includes a logic circuit and a memory circuit and has a plurality of input terminals and a plurality of output terminals. Signals are transmitted through the loop in a single specified direction in synchronization with a clock signal. Each of the macro circuits receives the signals at the input terminals thereof, accepts the signals if the signals are destined for the macro circuit, and transfers the signals to the output terminals thereof if the signals are not destined for the macro circuit. Even if the macro circuits simultaneously transmit signals, the electronic circuit system transmits the signals in the specified direction through the loop in synchronization with the clock signal up to destination macro circuits.
摘要翻译： 电子电路系统具有至少三个宏电路和用于将宏电路彼此连接成环路的多条信号线。 宏电路中的每一个包括逻辑电路和存储电路，并且具有多个输入端子和多个输出端子。 信号与时钟信号同步地在单个指定方向上通过环路传输。 每个宏电路在其输入端接收信号，如果信号指向宏电路，则接收信号，并且如果信号不是用于宏电路，则将信号传送到其输出端。 即使宏电路同时发送信号，电子电路系统也可以与到目标宏电路的时钟信号同步地通过环路在指定方向上发送信号。
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公开(公告)号：US07417884B2
公开(公告)日：2008-08-26
申请号：US11443030
申请日：2006-05-31
CPC分类号： G06F13/4243 , G11C5/066 , G11C7/1006
摘要： A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.
摘要翻译： 存储器控制器将每个由多个位组成的访问信号复用为光信号并输出复用的光信号。 此时，产生根据存储器件波长不同的光信号。 存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。 存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。 这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。 存储器接口单元不需要包括用于识别存储器件的解码电路。
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公开(公告)号：US20070192527A1
公开(公告)日：2007-08-16
申请号：US11443031
申请日：2006-05-31
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译： 半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。 用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。 通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。 因此，可以使用一种半导体存储器作为多种半导体存储器。 这消除了开发多种半导体存储器的需要，降低了开发成本。
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10.发明申请Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof 失效定时控制器和控制延迟电路，用于通过改变相位来控制信号的定时或延迟时间公开(公告)号：US20070188210A1
公开(公告)日：2007-08-16
申请号：US11723602
申请日：2007-03-21
申请人： Yoshinori Okajima
发明人： Yoshinori Okajima
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K5/135 , H03K2005/00039 , H03L7/0812
摘要： A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
摘要翻译： 受控延迟电路具有第一栅极链和第二栅极链。 第一栅极链用于测量第一控制信号的转换点和第二控制信号的转换点之间的时间差。 接收在第一门链中产生并表示时间差的第三信号的第二门链用于根据时间差从输入到输出提供适当的延迟时间。 受控延迟电路能够根据控制信号的周期适当地控制控制信号的定时。
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