公开(公告)号：US20060102947A1

公开(公告)日：2006-05-18

申请号：US11290432

申请日：2005-12-01

Applicant: Yung Wu

Inventor： Yung Wu

IPC: H01L29/94

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L27/10867 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66181

Abstract: A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the trench above the buried plate region in the substrate, where the first doped region contains carbon and the second doped region contains germanium provided in a portion of the first region, a dielectric layer formed on the bottom and sidewall of the trench, at least one polysilicon layer deposited in the trench and on the dielectric layer to cover the dielectric layer, and a transistor formed on a surface of the semiconductor substrate.

公开(公告)号：US20060043373A1

公开(公告)日：2006-03-02

申请号：US10984745

申请日：2004-11-10

Applicant: Yung Wu ,  Chun Cheng ,  Yung Yeh

Inventor： Yung Wu ,  Chun Cheng ,  Yung Yeh

IPC: H01L29/04

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/3244 ,  H01L27/3248 ,  H01L29/78621 ,  H01L51/5203 ,  H01L51/56 ,  H01L2251/5315

Abstract: A process for manufacturing a pixel array of top-emitting OLED pixel is provided. The process comprises: providing a substrate having at least two poly-silicon islands defined thereon, and defining an implantation region on the substrate; forming a gate insulator layer and a gate metal layer sequentially, and then defining a gate; carrying out an implantation process for forming the doped region; forming an inter-layer dielectric (ILD) layer and etching a plurality of contact holes thereon; forming a source/drain metal layer and defining a source/drain pattern thereon; wherein the patterned source/drain metal layer extends to the pixel array of the top-emitting OLED so as to be employed as a bottom electrode of the top-emitting OLED. The characteristic of the present invention is that the bottom electrode is substantially the portion of the source/drain extending to the pixel array of the top-emitting OLED, so that the array manufacturing can save at least two masks.

Abstract translation: 提供了一种用于制造顶部发光OLED像素的像素阵列的工艺。 该方法包括：提供其上限定有至少两个多硅岛的衬底，并在衬底上限定注入区; 依次形成栅极绝缘体层和栅极金属层，然后限定栅极; 进行用于形成掺杂区域的注入工艺; 形成层间介电层（ILD）层并在其上蚀刻多个接触孔; 形成源极/漏极金属层并在其上限定源极/漏极图案; 其中图案化源极/漏极金属层延伸到顶部发射OLED的像素阵列，以便用作顶部发光OLED的底部电极。 本发明的特征在于，底部电极基本上是源极/漏极延伸到顶部发射OLED的像素阵列的部分，使得阵列制造可以节省至少两个掩模。

公开(公告)号：US20060035400A1

公开(公告)日：2006-02-16

申请号：US11002282

申请日：2004-12-03

Applicant: Yung Wu ,  Tzu Tsai

Inventor： Yung Wu ,  Tzu Tsai

IPC: H01L21/00 ,  H01L23/58

CPC classification number: H01L31/202 ,  G01N27/414 ,  H01L27/14692 ,  H01L29/42384 ,  H01L29/4908 ,  H01L31/115 ,  Y02E10/50 ,  Y02P70/521

Abstract: The present invention discloses an apparatus of ion sensitive thin film transistor and method of manufacturing of the same. The apparatus of the invention, formed on a glass substrate, comprises an ion detector, formed on said glass substrate, including a plurality of ion sensitive transistors and a signal processor with display, also formed on said glass substrate, being coupled with said ion detector. The signal processor with display further comprises a circuit of signal processing, a driver circuit, and a display, wherein by means of the method of Low Temperature PolySilicon, i.e. LTPS technology, the invention integrates said ion detector and said signal processor with display on said glass substrate to become an tiny, light and thin apparatus with portable and disposable characteristics.

Abstract translation: 本发明公开了一种离子敏感薄膜晶体管的装置及其制造方法。 形成在玻璃基板上的本发明的装置包括形成在所述玻璃基板上的离子检测器，该离子检测器包括多个离子敏感晶体管和具有显示器的信号处理器，其也形成在所述玻璃基板上，与所述离子检测器 。 具有显示器的信号处理器还包括信号处理电路，驱动器电路和显示器，其中借助于低温多硅（即LTPS技术）的方法，本发明将所述离子检测器和所述信号处理器与所述 玻璃基板成为具有便携和一次性特征的微小，轻薄的设备。

公开(公告)号：US20050219215A1

公开(公告)日：2005-10-06

申请号：US10814147

申请日：2004-04-01

Applicant: Yung Wu

Inventor： Yung Wu

IPC: G09G5/00 ,  H05K1/02 ,  H05K1/18

CPC classification number: G06F3/0317 ,  H05K1/0274 ,  H05K1/18 ,  H05K2201/09072 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10462

Abstract: An optical mouse has a housing, a printed circuit board, a light source unit, a photodetector unit, a light-guiding unit and a lens unit. The light source unit has different colors of image light sources and is disposed on the printed circuit board. The light-guiding unit is arranged in the housing and adjacent to the light source unit for guiding a non-complementary color light relative to a reflection surface from one of the image light sources to the reflection surface. The lens unit is arranged in the housing and positioned below the photodetector unit for converging a reflected light reflected by the reflection surface into the photodetector unit. Furthermore, the optical mouse can be operated on various colors of reflection surfaces, and still retains better sensitivity.

Abstract translation: 光学鼠标具有壳体，印刷电路板，光源单元，光电检测器单元，导光单元和透镜单元。 光源单元具有不同的图像光源颜色，并且布置在印刷电路板上。 导光单元布置在壳体中并且与光源单元相邻，用于相对于从图像光源中的一个到反射表面的反射表面引导非互补色光。 透镜单元布置在壳体中并且位于光电检测器单元下方，用于将由反射表面反射的反射光会聚到光电检测器单元中。 此外，光学鼠标可以以各种颜色的反射表面操作，并且仍然保持更好的灵敏度。

公开(公告)号：US20050200076A1

公开(公告)日：2005-09-15

申请号：US10797021

申请日：2004-03-11

Applicant: Yung Wu

Inventor： Yung Wu

IPC: A63F9/06 ,  A63F9/10

CPC classification number: A63F9/10 ,  A63F9/0666 ,  A63F2009/1005

Abstract: A puzzle includes a base board on which set a number of cutouts, and the same number of puzzle pieces with shapes corresponding to the cutouts and images on both sides. With images on both sides of the puzzle pieces, the present invention provides two different jigsaw puzzles for assembly.

Abstract translation: 拼图包括设置多个切口的基板，以及具有与两侧的切口和图像相对应的形状的相同数量的拼图块。 利用拼图的两侧的图像，本发明提供了两个用于组装的不同拼图。

公开(公告)号：US5173617A

公开(公告)日：1992-12-22

申请号：US391689

申请日：1989-08-10

Applicant: Mitchell Alsup ,  Carl S. Dobbs ,  Yung Wu ,  Claude Moughanni ,  Elie I. Haddad

Inventor： Mitchell Alsup ,  Carl S. Dobbs ,  Yung Wu ,  Claude Moughanni ,  Elie I. Haddad

IPC: H03K5/26 ,  H03L7/081 ,  H03L7/089 ,  H04L7/033

CPC classification number: H03L7/0814 ,  H03K5/26 ,  H03L7/089 ,  H04L7/0337

Abstract: A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.

Abstract translation: 数字锁相环，不依赖于用于锁相的压控振荡器（VCO）。 用锁存器终止的相位检测器（PD）控制用于对延迟线上的延迟增加/减少进行编程的上/下计数器。 延迟线的抽头输出通过两相发生器，该相位发生器又反馈到PD以与参考时钟进行比较。 重复该过程直到获得相位锁定。