公开(公告)号：US4207528A

公开(公告)日：1980-06-10

申请号：US12090

申请日：1979-02-14

申请人： Akira Sawai

发明人： Akira Sawai

IPC分类号： H04L25/40 ,  H04L7/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L25/497 ,  H04L25/60 ,  H03K11/00 ,  H04B3/36

CPC分类号： H04L7/0062 ,  H04L7/027

摘要： A timing-phase control system provided on the receiving side of a duobinary transmission system is adaptable to high-speed PCM repeater systems using a wide-band transmission medium such as a coaxial cable. The system includes a discriminating and regenerating circuit for recovering the transmitted digital signal by discriminating and regenerating in an appropriate timing phase based on an input equalized duobinary waveform, a phase varying circuit for varying the phase of a timing signal externally supplied to the discriminating and regenerating circuit, and a derivative waveform generating circuit. In one embodiment, the derivative waveform generating circuit is responsive to the output of the discriminating and regenerating circuit, and a multiplier multiplies the output of the derivative waveform generating circuit and the equalized duobinary waveform by each other in a predetermined phase relationship. In another embodiment, the derivative waveform generating circuit differentiates the equalized duobinary waveform on a time scale, and a multiplier multiplies the output of this differentiating circuit and that of the discriminating and regenerating circuit in a predetermined phase relationship. In either case, a low-pass amplifier amplifies the output of the multiplier to provide, with a suitable D.C. offset, a negative feedback signal to the phase varying circuit.

摘要翻译： 在双二进制传输系统的接收侧设置的定时相位控制系统适用于使用诸如同轴电缆的宽带传输介质的高速PCM中继器系统。 该系统包括识别和再生电路，用于基于输入的均衡二进制波形在适当的定时相位中鉴别和再生来恢复所发送的数字信号;相变电路，用于改变外部提供给识别和再生的定时信号的相位 电路和导数波形发生电路。 在一个实施例中，导数波形发生电路响应鉴别和再生电路的输出，乘法器将导数波形发生电路的输出和均衡的双二进制波形以预定的相位关系彼此相乘。 在另一实施例中，微分波形发生电路使均衡的双二进制波形在时间尺度上进行微分，并且乘法器将该微分电路的输出与鉴别和再生电路的输出以预定的相位关系相乘。 在任一种情况下，低通放大器放大乘法器的输出，以将适当的直流偏移提供给相变电路的负反馈信号。

公开(公告)号：US20130169920A1

公开(公告)日：2013-07-04

申请号：US13822301

申请日：2012-01-26

申请人： Masanori Wada

发明人： Masanori Wada

IPC分类号： G02F1/1335

CPC分类号： G02F1/133526 ,  C03B23/037 ,  G02B1/041 ,  G02B3/14 ,  G02B6/3538 ,  G02B26/004 ,  G02F1/1313 ,  G02F1/1333 ,  G02F1/1341 ,  G02F1/13471 ,  G02F1/29 ,  G02F2001/133302 ,  G02F2001/294 ,  Y02P40/57

摘要： Provided are a method for manufacturing a liquid crystal lens which, even with the use of a thin sheet glass as a glass sheet for dividing a liquid crystal layer, can reduce the likelihood of breakage of the thin sheet glass in the production process and the liquid crystal lens. A mother liquid crystal lens having a plurality of liquid crystal lens units arrayed in a longitudinal direction thereof is cut for each of the liquid crystal lens units to separate out the liquid crystal lens units and thus manufacture respective liquid crystal lenses 10. Longitudinally extending side surfaces 13c, 13d, 14c, and 14d of glass ribbons which provide thin sheet glasses 13 and 14 have an outwardly bulging curved shape in a cross section perpendicular to the longitudinal direction.

摘要翻译： 提供一种制造液晶透镜的方法，即使使用薄板玻璃作为用于分割液晶层的玻璃板，也可以减少在制造过程中薄板玻璃的破裂的可能性，液体 水晶镜头。 对于每个液晶透镜单元切割具有沿其纵向方向排列的多个液晶透镜单元的母液晶透镜，以分离出液晶透镜单元，从而制造各自的液晶透镜10.纵向延伸的侧表面 提供薄片玻璃13和14的玻璃带的13c，13d，14c和14d在垂直于纵向方向的横截面中具有向外凸出的弯曲形状。

公开(公告)号：US4727484A

公开(公告)日：1988-02-23

申请号：US945991

申请日：1986-12-24

申请人： Masato Saito

发明人： Masato Saito

IPC分类号： G06F12/10 ,  G06F9/38 ,  G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0848

摘要： A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.

摘要翻译： 用于使用虚拟存储器技术的数据处理器的存储器控​​制装置包括两个高速缓存存储器，一个用于存储位于主存储器（MMU）中的指令的一部分，另一个用于存储位于主存储器中的操作数数据的一部分。 单独的翻译旁边缓冲器（TLB）连接到每个高速缓冲存储器，其中TLB连接到高速缓存存储器，其存储指令，其操作以将逻辑地址转换为MMU存储指令中的实际地址，而连接到高速缓冲存储器的TLB存储操作数 用于将逻辑地址转换为存储操作数数据的MMU中的实际地址的数据。

公开(公告)号：US4717846A

公开(公告)日：1988-01-05

申请号：US912197

申请日：1986-09-25

申请人： Manabu Ando

发明人： Manabu Ando

IPC分类号： H03F3/30 ,  H03F3/20 ,  H03F3/34 ,  H03F3/345 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/00 ,  H03K19/20

CPC分类号： H03K19/00315

摘要： An output circuit protected by an abnormal voltage supplied at an output terminal is disclosed. The output circuit comprises a first switching circuit includes first and second transistors connected in series for providing an output terminal with a first potential therethrough in response to a first logic state of a logic signal, a second switching circuit for providing the output terminal with a second potential in response to a second logic state of the logic signal, and means for making the first and second transistors non-conducting when the first switching circuit is disenabled.

摘要翻译： 公开了一种由输出端提供的异常电压保护的输出电路。 输出电路包括第一开关电路，其包括串联连接的第一和第二晶体管，用于响应于逻辑信号的第一逻辑状态提供具有第一电位的输出端，第二开关电路用于向输出端提供第二 响应于逻辑信号的第二逻辑状态的电位，以及用于当第一开关电路不被使能时使第一和第二晶体管不导通的装置。

公开(公告)号：US4644322A

公开(公告)日：1987-02-17

申请号：US435965

申请日：1982-10-22

申请人： Tsuneo Fujita

发明人： Tsuneo Fujita

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M7/16

CPC分类号： H03M1/1071 ,  H03M1/361

摘要： A parallel comparison type A/D converter comprises a voltage divider having 2.sup.N divider junctions connected in series between a reference voltage terminal and a ground potential terminal, 2.sup.N comparators for receiving as reference voltages the outputs of the respective divider junctions, a position detection logic circuit for receiving the outputs of the comparators, an encoder for receiving the output of the position detection logic circuit, and a code converter for receiving the output of the first digital encoder. The encoder adopts the Gray code format, and the code converter converts the Gray code format into the binary code format.

摘要翻译： 并联比较型A / D转换器包括：一个分压器，具有2N个分压器串联连接在一个参考电压端子和一个地电位端子之间; 2N个比较器，用于接收相应的分压器结点的输出作为参考电压，一个位置检测逻辑电路 用于接收比较器的输出，用于接收位置检测逻辑电路的输出的编码器和用于接收第一数字编码器的输出的代码转换器。 编码器采用格雷码格式，代码转换器将格雷码格式转换为二进制码格式。

公开(公告)号：US4635088A

公开(公告)日：1987-01-06

申请号：US661837

申请日：1984-10-17

申请人： Hirotugu Eguchi

发明人： Hirotugu Eguchi

IPC分类号： H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H03K19/017 ,  H03K19/0944 ,  H01L29/78 ,  H01L23/48 ,  H01L27/02

CPC分类号： H01L27/088 ,  H03K19/017 ,  H03K19/09441

摘要： An improved semiconductor device operable at a high-speed and with a low power consumption is disclosed. The device comprises a common impurity-doped region, a first insulated gate field effect transistor utilizing the common impurity-doped region as a drain thereof, a second insulated gate field effect transistor utilizing the common impurity-doped region as a drain thereof, control means for controlling switching operations of the first and second transistor at the same time and means for deriving an output signal from the common impurity-doped region.

摘要翻译： 公开了一种以高速和低功耗工作的改进的半导体器件。 该器件包括公共杂质掺杂区域，利用公共杂质掺杂区域作为其漏极的第一绝缘栅场效应晶体管，利用公共杂质掺杂区域作为漏极的第二绝缘栅场效应晶体管，控制装置 用于同时控制第一和第二晶体管的开关操作和用于从公共杂质掺杂区域导出输出信号的装置。

公开(公告)号：US4592993A

公开(公告)日：1986-06-03

申请号：US787695

申请日：1985-10-15

申请人： Yoshitake Ohnishi ,  Takeshi Endo

发明人： Yoshitake Ohnishi ,  Takeshi Endo

IPC分类号： G03F7/038 ,  G03C5/00

CPC分类号： G03F7/038

摘要： A process for fabrication of resist comprising a substrate and an overlying radiation sensitive layer, said overlying layer consisting essentially of a specific polymer or copolymer of vinylnaphthalene.

摘要翻译： 一种用于制造抗蚀剂的方法，包括基底和上覆的辐射敏感层，所述上覆层基本上由乙烯基萘的特定聚合物或共聚物组成。

公开(公告)号：US4592086A

公开(公告)日：1986-05-27

申请号：US447829

申请日：1982-12-08

申请人： Masao Watari ,  Hiroaki Sakoe

发明人： Masao Watari ,  Hiroaki Sakoe

IPC分类号： G10L15/12 ,  G10L5/06

CPC分类号： G10L15/12

摘要： A continuous speech recognition system determines the similarity between input patterns and reference patterns over time such that similarities between previously spoken speech patterns and reference patterns are determined while speech continues to be spoken. Degrees of dissimilarity at arbitrary reference pattern word times are determined asymptotically and are recorded. The minimum degree of dissimilarity is determined and the corresponding word is categorized. Recognition decisions are ultimately made in reverse chronological order.

摘要翻译： 连续语音识别系统确定输入模式和参考模式随时间的相似性，使得在语音继续被说出的同时确定先前说出的语音模式和参考模式之间的相似性。 任意参考模式字时间的不相似度渐近确定并被记录。 确定最小程度的不相似性并对相应的词进行分类。 识别决定最终按照时间顺序排列。

公开(公告)号：US4571502A

公开(公告)日：1986-02-18

申请号：US446865

申请日：1982-12-06

申请人： Tadakatsu Kimura ,  Takayoshi Makabe ,  Yoshiaki Kuraishi

发明人： Tadakatsu Kimura ,  Takayoshi Makabe ,  Yoshiaki Kuraishi

IPC分类号： G05F1/56 ,  G01R19/22 ,  H03K5/00 ,  H03F3/16

CPC分类号： G01R19/22

摘要： A full wave rectifier comprises an input terminal supplied with an AC signal and an output terminal for delivering a rectified DC signal. An operational amplifier having an inverting input terminal, amplifies the AC signal. A rectifier gain setting is provided by a first resistor connected between the input terminal and the inverting terminal of the amplifier. A second resistor, having the same resistance as the first resistor, is connected between the inverting terminal and output terminal of the amplifier. A depletion type MOS FET operates responsive to the output of the amplifier, for performing a switching operation.

摘要翻译： 全波整流器包括提供有AC信号的输入端和用于传送整流的DC信号的输出端。 具有反相输入端的运算放大器放大AC信号。 整流器增益设置由连接在放大器的输入端和反相端之间的第一电阻器提供。 具有与第一电阻器相同的电阻的第二电阻器连接在放大器的反相端子和输出端子之间。 耗尽型MOS FET响应于放大器的输出而工作，用于执行开关操作。

公开(公告)号：US4570083A

公开(公告)日：1986-02-11

申请号：US457596

申请日：1983-01-13

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： G11C11/417 ,  G11C7/12 ,  G11C11/41 ,  H03K19/003 ,  H03K19/096 ,  H03K17/16 ,  H03K17/693

CPC分类号： H03K19/00361 ,  G11C7/12

摘要： A precharge circuit which suppresses a peak of a charge current in conducting a precharge operation is disclosed.The precharge circuit comprises a precharge transistor for feeding the precharge current and means for generating a precharge control signal which changes slowly only when the precharge control signal is near an intermediate level of the specified binary levels of the precharge signal and changes quickly when the precharge control signal is not near the intermediate level.

摘要翻译： 公开了一种在进行预充电操作时抑制充电电流的峰值的预充电电路。 预充电电路包括用于馈送预充电电流的预充电晶体管和用于产生仅当预充电控制信号接近预充电信号的指定二进制电平的中间电平时缓慢变化的预充电控制信号的装置，并且当预充电控制 信号不在中间水平附近。