公开(公告)号：US08680600B2

公开(公告)日：2014-03-25

申请号：US13337810

申请日：2011-12-27

申请人： Yukihiro Nagai

发明人： Yukihiro Nagai

IPC分类号： H01L27/108

CPC分类号： H01L27/10876 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors. The pillars are aligned in a straight line in a first direction and have respectively a primary control wall along the first direction and two ancillary control walls perpendicular to the primary control wall. The gate line is connected to the primary control wall in the first direction through a first isolated layer. The conductors are interposed between the ancillary control walls through second isolated layers. By providing the gate line merely on the primary control wall and the conductors to aid the gate line to control ON/OFF of the pillars, problems of etching and separating gate material during gradually shrunken feature size process that are difficult to control etching positions and etching duration can be prevented.

摘要翻译： 垂直晶体管结构包括衬底，位于衬底上的多个柱，并且在选定距离处彼此间隔开，栅极线和多个导体。 支柱在第一方向上以直线排列，并且分别具有沿着第一方向的主控制壁和垂直于主控制壁的两个辅助控制壁。 栅极线通过第一隔离层在第​​一方向连接到主控制壁。 导体通过第二隔离层介于辅助控制壁之间。 通过仅在主控制壁和导体上提供栅极线以帮助栅极线控制柱的ON / OFF，在逐渐缩小的特征尺寸过程中蚀刻和分离栅极材料的问题难以控制蚀刻位置和蚀刻 可以防止持续时间。

公开(公告)号：US08470657B1

公开(公告)日：2013-06-25

申请号：US13532293

申请日：2012-06-25

申请人： Chih-Hsin Lo

发明人： Chih-Hsin Lo

IPC分类号： H01L21/8238 ,  H01L21/425 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L21/2254 ,  H01L21/02299 ,  H01L27/10876 ,  H01L27/10885

摘要： An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.

摘要翻译： 一种用于半导体侧壁的离子注入方法包括以下步骤：在衬底上形成沟槽，并且所述沟槽具有下反射层和邻近底部的两个侧壁; 执行等离子体掺杂方法以将导电离子溅射到下反射层，并且导电离子从下反射层反弹以粘附到侧壁以在其上分别形成粘合层; 并执行退火程序以将粘附层的导电离子扩散到衬底中以形成导电段。 因此，在不损坏衬底的情况下，在预定区域形成具有高导电离子掺杂浓度的导电段，以满足半导体设计要求。

公开(公告)号：US08921911B2

公开(公告)日：2014-12-30

申请号：US13609739

申请日：2012-09-11

申请人： Pin-Yuan Yu ,  Yi-Chun Shao ,  Chien-Hua Chu

发明人： Pin-Yuan Yu ,  Yi-Chun Shao ,  Chien-Hua Chu

IPC分类号： H01L27/108

CPC分类号： H01G4/005 ,  H01G4/33 ,  H01L28/92

摘要： A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.

摘要翻译： 垂直半导体电荷存储结构包括衬底，至少一个下电极，电介质层和上电极。 下电极包括下导体和连接到下导体的第一侧导体和第二侧导体。 第一侧导体和第二侧导体彼此平行并与下导体形成夹角。 第一侧导体与衬底的高度大于第二侧导体与衬底的高度。 电介质层和上电极依次形成在基板和下电极的表面上。 因此，通过以不同的高度形成第一侧导体和第二侧导体，增加开口率以减少后续处理中的填充或沉积的困难，以进一步提高总的屈服率。

公开(公告)号：US08673730B2

公开(公告)日：2014-03-18

申请号：US13301255

申请日：2011-11-21

申请人： Pei-Chun Hung ,  Li-Hsun Chen ,  Chien-hua Tsai ,  Masahiko Ohuchi ,  Sheng-chang Liang

发明人： Pei-Chun Hung ,  Li-Hsun Chen ,  Chien-hua Tsai ,  Masahiko Ohuchi ,  Sheng-chang Liang

IPC分类号： H01L21/20

CPC分类号： H01L28/92 ,  H01L27/1085

摘要： A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

摘要翻译： 制造充电容量结构的方法包括以下步骤：依次在基板上形成第一氧化物层，支撑层和第二氧化物层; 在所述第二氧化物层的表面上以矩阵形成多个蚀刻孔以穿过所述基板，所述蚀刻孔以选定距离彼此间隔开; 在蚀刻孔中形成多个柱层; 通过蚀刻去除第二氧化物层; 在支撑层和支柱管的表面上形成蚀刻保护层，其形成为蚀刻孔之间间隔距离的一半的厚度，使得在对角线位置处的柱管形成自校准孔; 最后通过蚀刻从自校准孔中除去第一氧化物层。 通过自校准孔，本发明不需要提供额外的光致抗蚀剂来形成孔。

公开(公告)号：US08546220B1

公开(公告)日：2013-10-01

申请号：US13551919

申请日：2012-07-18

申请人： Isao Tanaka ,  Chien-hua Tsai

发明人： Isao Tanaka ,  Chien-hua Tsai

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/10885 ,  H01L27/1203

摘要： A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.

摘要翻译： 一种用于制造掩埋位线的方法包括以下步骤：限定多个平行掩蔽区域和多个第一蚀刻区域，每个第一蚀刻区域形成在衬底的表面上的任何两个相邻的掩蔽区域之间，并且其中所述掩蔽区域比所述第一蚀刻区域宽 蚀刻区域 蚀刻第一蚀刻区域以形成多个第一沟槽和多个第一柱; 分别在每个第一沟槽的两个侧壁上形成两个位线; 蚀刻第一柱以形成对应于位线的多个第二柱。 本发明使用两级蚀刻工艺来防止柱由于高纵横比而弯曲或折叠。 此外，本发明具有简单的过程，并且能够降低成本并减小单元尺寸。

公开(公告)号：US08956961B2

公开(公告)日：2015-02-17

申请号：US13415959

申请日：2012-03-09

申请人： Kazuaki Takesako ,  Wen-Kuei Hsu ,  Yoshinori Tanaka ,  Yukihiro Nagai ,  Chih-Wei Hsiung ,  Hirotake Fujita ,  Tomohiro Kadoya ,  Wei-Chih Liu ,  Hsuan-Yu Fang ,  Yu-Ling Huang ,  Meng-Hsien Chen ,  Chun-Chiao Tseng ,  Chung-Yung Ai ,  Yu-Shan Hsu ,  Wei-Che Chang ,  Chun-Hua Huang

发明人： Kazuaki Takesako ,  Wen-Kuei Hsu ,  Yoshinori Tanaka ,  Yukihiro Nagai ,  Chih-Wei Hsiung ,  Hirotake Fujita ,  Tomohiro Kadoya ,  Wei-Chih Liu ,  Hsuan-Yu Fang ,  Yu-Ling Huang ,  Meng-Hsien Chen ,  Chun-Chiao Tseng ,  Chung-Yung Ai ,  Yu-Shan Hsu ,  Wei-Che Chang ,  Chun-Hua Huang

IPC分类号： H01L21/02

CPC分类号： H01L21/2257 ,  H01L21/2236 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.

摘要翻译： 半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

公开(公告)号：US08679213B2

公开(公告)日：2014-03-25

申请号：US13282905

申请日：2011-10-27

申请人： Chin Hsiu Lu ,  Chin Ming Wang

发明人： Chin Hsiu Lu ,  Chin Ming Wang

IPC分类号： B01D45/00

CPC分类号： B01D45/08

摘要： A dust collector for catching dust generated by temperature drop comprises a box, a plurality of separating boards, a plurality of catch boards, and a plurality of baffle boards. The separating boards partition the box to form an air flow channel. The catch boards and the baffle boards are staggered in the air flow channel; a portion of the catch boards are arranged in a central column to form a superimposition region along the vertical direction. The pores of the catch boards in the superimposition region are overlapped to make the air flow pour into the air flow channel easily. The baffle boards are staggered at the left or right of the catch boards, whereby the air flow takes more time to have a longer travel in the air flow channel, and dust is not accumulated in a single area but uniformly caught by the catch boards.

摘要翻译： 用于捕捉由温降引起的尘埃的集尘器包括箱体，多个分隔板，多个捕获板和多个挡板。 分离板分隔箱以形成气流通道。 挡板和挡板在空气流动通道中交错; 捕获板的一部分布置在中心柱中以沿着垂直方向形成叠加区域。 重叠区域中的卡扣板的孔重叠，容易使空气流入空气流动通道。 挡板在捕获板的左侧或右侧交错，由此空气流在空气流动通道中需要更长的时间以更长的行程，并且灰尘不会积聚在单个区域中，而是被捕获板均匀地捕获。

公开(公告)号：US08618591B2

公开(公告)日：2013-12-31

申请号：US13455371

申请日：2012-04-25

申请人： Yukihiro Nagai

发明人： Yukihiro Nagai

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10891 ,  H01L27/0203 ,  H01L27/10885 ,  H01L27/10888

摘要： A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars.

摘要翻译： 半导体器件包括：具有基底和包括多个支柱的柱阵列的基板; 多个位线，每个位线设置在柱阵列的两个相邻列之间; 多个字线，每个字线连接到柱阵列的相应行之一; 以及包括以行和列排列的多个位线接点的接触阵列。 接触阵列的每列的位线触点嵌入在基座中并且电连接到相应的一个位线。 每个位线触点与相应的一个位线相交并且在两个相邻的柱之间延伸并且电连接到两个相邻的柱。

公开(公告)号：US08437184B1

公开(公告)日：2013-05-07

申请号：US13312074

申请日：2011-12-06

申请人： Chih-Wei Hsiung

发明人： Chih-Wei Hsiung

IPC分类号： G11C11/34

CPC分类号： H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： A method of controlling a vertical dual-gate DRAM provides a short circuit state, a clearing state and a false broken circuit state. In the short circuit state, a first gate and a second gate at two sides of a first pillar are controlled to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar. In the clearing state, the first gate and second gate are controlled to respectively have a clearing voltage to disconnect electric connection between the drain and source at two ends of the first pillar. The false broken circuit state is entered after the clearing state has been finished. The invention does not separate gates between neighboring pillars, but controls ON/OFF of transistors electrically so that no current leakage is generated in the clearing state and problem of inaccurate data reading can be prevented.

摘要翻译： 控制垂直双栅极DRAM的方法提供短路状态，清零状态和假断路状态。 在短路状态下，控制第一支柱两侧的第一栅极和第二栅极分别具有导通电压，以在第一支柱的两端形成漏极与源极之间的电连接。 在清除状态下，控制第一栅极和第二栅极分别具有清除电压，以在第一支柱的两端断开漏极和源极之间的电连接。 在清除状态结束后进入错误的断路状态。 本发明不在相邻柱之间分隔栅极，而是电连接晶体管的导通/截止，从而在清除状态下不产生电流泄漏，并且可以防止数据读取不准确的问题。

公开(公告)号：US08377813B2

公开(公告)日：2013-02-19

申请号：US12870612

申请日：2010-08-27

申请人： Chih-Hao Lin

发明人： Chih-Hao Lin

IPC分类号： H01L21/3205

CPC分类号： H01L27/10891 ,  H01L21/3083 ,  H01L27/10876 ,  H01L29/66666

摘要： A method for forming a buried split word line structure is provided. The method comprises the following steps. At first, a substrate having a trench therein is provided. Two liners are formed to a first thickness on sidewalls of the trench. Then, the trench is filled with a first insulating layer to a first height. The two liners are removed. Finally, a conductive material is deposited to a second height between and adjacent to the first insulating layer and the trench. Here, the first height is greater than the second height.

摘要翻译： 提供了一种用于形成掩埋分割字线结构的方法。 该方法包括以下步骤。 首先，提供其中具有沟槽的衬底。 两个衬垫在沟槽的侧壁上形成为第一厚度。 然后，将沟槽填充到第一高度的第一绝缘层。 两个衬垫被移除。 最后，将导电材料沉积到第一绝缘层和沟槽之间的第二高度上并与其相邻。 这里，第一高度大于第二高度。